ICCD C

81 papers

YearTitle / Authors
200927th International Conference on Computer Design, ICCD 2009, Lake Tahoe, CA, USA, October 4-7, 2009
20093D GPU architecture using cache stacking: Performance, cost, power and thermal analysis.
Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Vijay Narayanan, Yuan Xie
20093D simulation and analysis of the radiation tolerance of voltage scaled digital circuit.
Rajesh Garg, Sunil P. Khatri
20093D stacked power distribution considering substrate coupling.
Amirali Shayan Arani, Xiang Hu, Wanping Zhang, Chung-Kuan Cheng, A. Ege Engin, Xiaoming Chen, Mikhail Popovich
2009A PLL design based on a standing wave resonant oscillator.
Vinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri
2009A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes.
Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun
2009A disruptive computer design idea: Architectures with repeatable timing.
Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Isaac Liu, Hiren D. Patel, Martin Schoeberl
2009A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems.
Jason D. Lee, Rabi N. Mahapatra, Praveen Bhojwani
2009A fast routability- and performance-driven droplet routing algorithm for digital microfluidic biochips.
Tsung-Wei Huang, Tsung-Yi Ho
2009A flexible communication scheme for rationally-related clock frequencies.
Jean-Michel Chabloz, Ahmed Hemani
2009A hierarchical approach towards system level static timing verification of SoCs.
Rupsa Chakraborty, Dipanwita Roy Chowdhury
2009A high throughput FFT processor with no multipliers.
Shakeel S. Abdulla, Haewoon Nam, Mark McDermot, Jacob A. Abraham
2009A new verification method for embedded systems.
Robert A. Thacker, Chris J. Myers, Kevin R. Jones, Scott Little
2009A novel SoC architecture on FPGA for ultra fast face detection.
Chun He, Alexandros Papakonstantinou, Deming Chen
2009A power-aware hybrid RAM-CAM renaming mechanism for fast recovery.
Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López
2009A radiation tolerant Phase Locked Loop design for digital electronics.
Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri
2009A robust pulsed flip-flop and its use in enhanced scan design.
Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri
2009Accelerating mobile augmented reality on a handheld platform.
Seung Eun Lee, Yong Zhang, Zhen Fang, Sadagopan Srinivasan, Ravi Iyer, Donald Newell
2009Accurate estimation of vector dependent leakage power in the presence of process variations.
Romana Fernandes, Ranga Vemuri
2009Adaptive online testing for efficient hard fault detection.
Shantanu Gupta, Amin Ansari, Shuguang Feng, Scott A. Mahlke
2009Algorithmic approach to designing an easy-to-program system: Can it lead to a HW-enhanced programmer's workflow add-on?
Uzi Vishkin
2009Analysis and optimization of pausible clocking based GALS design.
Xin Fan, Milos Krstic, Eckhard Grass
2009Automatic synthesis of computation interference constraints for relative timing verification.
Yang Xu, Ken S. Stevens
2009Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling.
Jiayuan Meng, Kevin Skadron
2009Code density concerns for new architectures.
Vincent M. Weaver, Sally A. McKee
2009ColSpace: Towards algorithm/implementation co-optimization.
Jiawei Huang, John C. Lach
2009Compiler-directed leakage reduction in embedded microprocessors.
Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori
2009Computational bit-width allocation for operations in vector calculus.
Adam B. Kinsman, Nicola Nicolici
2009Computer-aided design for microfluidic chips based on multilayer soft lithography.
Nada Amin, William Thies, Saman P. Amarasinghe
2009Defect-based test optimization for analog/RF circuits for near-zero DPPM applications.
Ender Yilmaz, Sule Ozev
2009Design and test strategies for microarchitectural post-fabrication tuning.
Xiaoyao Liang, Benjamin C. Lee, Gu-Yeon Wei, David M. Brooks
2009Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors.
Nasir Mohyuddin, Kimish Patel, Massoud Pedram
2009Efficient architectures for elliptic curve cryptography processors for RFID.
Lawrence Leinweber, Christos A. Papachristou, Francis G. Wolff
2009Efficient binary translation system with low hardware cost.
Weiwu Hu, Qi Liu, Jian Wang, Songsong Cai, Menghao Su, Xiaoyu Li
2009Efficient calibration of thermal models based on application behavior.
Youngwoo Ahn, Inchoon Yeo, Riccardo Bettati
2009Empirical performance models for 3T1D memories.
Kristen Lovin, Benjamin C. Lee, Xiaoyao Liang, David M. Brooks, Gu-Yeon Wei
2009Enabling resonant clock distribution with scaled on-chip magnetic inductors.
Saurabh Sinha, Wei Xu, Jyothi Bhaskarr Velamala, Tawab Dastagir, Bertan Bakkaloglu, Hongbin Yu, Yu Cao
2009Extending data prefetching to cope with context switch misses.
Hanyu Cui, Suleyman Sair
2009Fault-tolerant synthesis using non-uniform redundancy.
Keven L. Woo, Matthew R. Guthaus
2009FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing.
Chun-Yi Lee, Niraj K. Jha
2009Framework for massively parallel testing at wafer and package test.
A. Hakan Baba, Kee Sup Kim
2009Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study.
Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir
2009Impact analysis of performance faults in modern microprocessors.
Naghmeh Karimi, Michail Maniatakos, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris
2009Imperfection-immune Carbon Nanotube digital VLSI.
Nishant Patil, Subhasish Mitra
2009Interconnect performance corners considering crosstalk noise.
Ravikishore Gandikota, David T. Blaauw, Dennis Sylvester
2009Intra-vector SIMD instructions for core specialization.
Cor Meenderinck, Ben H. H. Juurlink
2009Iterative built-in testing and tuning of mixed-signal/RF systems.
Abhijit Chatterjee, Donghoon Han, Vishwanath Natarajan, Shyam Kumar Devarakond, Shreyas Sen, Hyun Woo Choi, Rajarajan Senguttuvan, Soumendu Bhattacharya, Abhilash Goyal, Deuk Lee, Madhavan Swaminathan
2009LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors.
Javier Lira, Carlos Molina, Antonio González
2009Low-overhead error detection for Networks-on-Chip.
Amit Berman, Idit Keidar
2009Mid-range wireless energy transfer using inductive resonance for wireless sensors.
Shahrzad Jalali Mazlouman, Alireza Mahanfar, Bozena Kaminska
2009Multiplier-less and table-less linear approximation for square and square-root.
In-Cheol Park, Tae-Hwan Kim
2009N-way ring and square arbiters.
Masashi Imai, Tomohiro Yoneda, Takashi Nanya
2009On improving the algorithmic robustness of a low-power FIR filter.
Sourabh Khire, Saibal Mukhopadhyay
2009On-chip bidirectional wiring for heavily pipelined systems using network coding.
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
2009Online multiple error detection in crossbar nano-architectures.
Navid Farazmand, Mehdi Baradaran Tahoori
2009Optical lithography simulation using wavelet transform.
Rance Rodrigues, Aswin Sreedhar, Sandip Kundu
2009Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design.
Mateja Putic, Liang Di, Benton H. Calhoun, John C. Lach
2009Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions.
Michael J. Anderson, Chuck Tsen, Liang-Kai Wang, Katherine Compton, Michael J. Schulte
2009Pragmatic design of gated-diode FinFET DRAMs.
Ajay N. Bhoj, Niraj K. Jha
2009Quality improvement and cost reduction using statistical outlier methods.
Amit Nahar, Kenneth M. Butler, John M. Carulli Jr., Charles Weinberger
2009Rapid early-stage microarchitecture design using predictive models.
Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle
2009Real-time, unobtrusive, and efficient program execution tracing with stream caches and last stream predictors.
Vladimir Uzelac, Aleksandar Milenkovic, Milena Milenkovic, Martin Burtscher
2009Reducing dynamic power dissipation in pipelined forwarding engines.
Weirong Jiang, Viktor K. Prasanna
2009Reducing register file size through instruction pre-execution enhanced by value prediction.
Yusuke Tanaka, Hideki Ando
2009Reincarnate historic systems on FPGA with novel design methodology.
Naohiko Shimizu
2009Reliable cache design with detection of gate oxide breakdown using BIST.
Fahad Ahmed, Linda S. Milor
2009Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design.
Hai Lin, Yunsi Fei
2009Reusing cached schedules in an out-of-order processor with in-order issue logic.
Oscar Palomar, Toni Juan, Juan J. Navarro
2009SHIELDSTRAP: Making secure processors truly secure.
Siddhartha Chhabra, Brian Rogers, Yan Solihin
2009Statistical timing analysis based on simulation of lithographic process.
Aswin Sreedhar, Sandip Kundu
2009Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.
Renshen Wang, Takumi Okamoto, Chung-Kuan Cheng
2009Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs.
Brandon Noia, Krishnendu Chakrabarty, Yuan Xie
2009Testing bio-chips.
Krishnendu Chakrabarty
2009The impact of liquid cooling on 3D multi-core processors.
Hyung Beom Jang, Ikroh Yoon, Cheol Hong Kim, Seungwon Shin, Sung Woo Chung
2009The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.
Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li
2009Timing variation-aware high-level synthesis considering accurate yield computation.
Jongyoon Jung, Taewhan Kim
2009Topology-driven cell layout migration with collinear constraints.
De-Shiun Fu, Ying-Zhih Chaung, Yen-Hung Lin, Yih-Lang Li
2009Transaction-based debugging of system-on-chips with patterns.
Amir Masoud Gharehbaghi, Masahiro Fujita
2009Using checksum to reduce power consumption of display systems for low-motion content.
Kyungtae Han, Zhen Fang, Paul Diefenbaugh, Richard Forand, Ravi R. Iyer, Donald Newell
2009VariPipe: Low-overhead variable-clock synchronous pipelines.
Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu
2009WHOLE: A low energy I-Cache with separate way history.
Zichao Xie, Dong Tong, Xu Cheng