ICCD C

107 papers

YearTitle / Authors
200826th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings
2008A dynamic accuracy-refinement approach to timing-driven technology mapping.
Sz-Cheng Huang, Jie-Hong Roland Jiang
2008A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications.
Adnan Suleiman, Hani Saleh, Adel Hussein, David Akopian
2008A fine-grain dynamic sleep control scheme in MIPS R3000.
Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura
2008A floating-point fused dot-product unit.
Hani H. Saleh, Earl E. Swartzlander Jr.
2008A high-performance parallel CAVLC encoder on a fine-grained many-core system.
Zhibin Xiao, Bevan M. Baas
2008A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions.
Dimitrios Bountas, Georgios I. Stamoulis, Nestoras E. Evmorfopoulos
2008A novel, highly SEU tolerant digital circuit design approach.
Rajesh Garg, Sunil P. Khatri
2008A parallel Steiner tree heuristic for macro cell routing.
Christian Fobel, Gary Gréwal
2008A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters.
Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann
2008A resource efficient content inspection system for next generation Smart NICs.
Karthik Sabhanatarajan, Ann Gordon-Ross
2008A simple latency tolerant processor.
Satyanarayana Nekkalapu, Haitham Akkary, Komal Jothi, Renjith Retnamma, Xiaoyu Song
2008A study of reliability issues in clock distribution networks.
Aida Todri, Malgorzata Marek-Sadowska
2008Accelerating search and recognition with a TCAM functional unit.
Atif Hashmi, Mikko H. Lipasti
2008Acceleration of a 3D target tracking algorithm using an application specific instruction set processor.
Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois
2008Acquiring an exhaustive, continuous and real-time trace from SoCs.
Christian Hochberger, Alexander Weiss
2008Adaptive SRAM memory for low power and high yield.
Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham
2008Adaptive techniques for leakage power management in L2 cache peripheral circuits.
Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot
2008An improved micro-architecture for function approximation using piecewise quadratic interpolation.
Shai Erez, Guy Even
2008Analysis and minimization of practical energy in 45nm subthreshold logic circuits.
David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
2008Ant Colony Optimization directed program abstraction for software bounded model checking.
Xueqi Cheng, Michael S. Hsiao
2008Application Specific Instruction set processor specialized for block motion estimation.
Marc-André Daigneault, J. M. Pierre Langlois, Jean-Pierre David
2008Applying speculation techniques to implement functional units.
Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado
2008Architecture implementation of an improved decimal CORDIC method.
José Luis Sánchez, Higinio Mora Mora, Jerónimo Mora Pascual, Antonio Jimeno
2008Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities.
Kaijian Shi
2008Bridging the gap between nanomagnetic devices and circuits.
Michael T. Niemier, Xiaobo Sharon Hu, Aaron Dingler, M. Tanvir Alam, Gary H. Bernstein, Wolfgang Porod
2008Characterization and design of sequential circuit elements to combat soft error.
Hamed Abrishami, Safar Hatami, Massoud Pedram
2008Characterization of granularity and redundancy for SRAMs for optimal yield-per-area.
Jae Chul Cha, Sandeep K. Gupta
2008Chip level thermal profile estimation using on-chip temperature sensors.
Yufu Zhang, Ankur Srivastava, Mohamed M. Zahran
2008Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes.
Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang
2008Comparative analysis of NBTI effects on low power and high performance flip-flops.
Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie
2008Configurable rectilinear Steiner tree construction for SoC and nano technologies.
Iris Hui-Ru Jiang, Yen-Ting Yu
2008Contention-aware application mapping for Network-on-Chip communication architectures.
Chen-Ling Chou, Radu Marculescu
2008Conversion driven design of binary to mixed radix circuits.
Ashur Rafiev, Julian P. Murphy, Danil Sokolov, Alexandre Yakovlev
2008CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework.
Andrea Pellegrini, Kypros Constantinides, Dan Zhang, Shobana Sudhakar, Valeria Bertacco, Todd M. Austin
2008Custom rotary clock router.
Vinayak Honkote, Baris Taskin
2008Design and evaluation of an optical CPU-DRAM interconnect.
Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella
2008Design of application-specific 3D Networks-on-Chip architectures.
Shan Yan, Bill Lin
2008Digital filter synthesis considering multiple adder graphs for a coefficient.
Jeong-Ho Han, In-Cheol Park
2008Dynamic test scheduling for analog circuits for improved test quality.
Ender Yilmaz, Sule Ozev
2008Dynamically reconfigurable soft output MIMO detector.
Pankaj Bhagawat, Rajballav Dash, Gwan Choi
2008ECO-Map: Technology remapping for post-mask ECO using simulated annealing.
Nilesh Modi, Malgorzata Marek-Sadowska
2008Early stage FPGA interconnect leakage power estimation.
Shilpa Bhoj, Dinesh Bhatia
2008Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective.
Venkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew, Tin-Fook Ngai
2008Energy-aware opcode design.
Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte
2008Energy-delay tradeoffs in 32-bit static shifter designs.
Steven Huntzicker, Michael Dayringer, Justin Soprano, Anthony Weerasinghe, David Money Harris, Dinesh Patil
2008Energy-precision tradeoffs in mobile Graphics Processing Units.
Jeff Pool, Anselmo Lastra, Montek Singh
2008Exploiting producer patterns and L2 cache for timely dependence-based prefetching.
Chungsoo Lim, Gregory T. Byrd
2008Exploiting spare resources of in-order SMT processors executing hard real-time threads.
Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer
2008Fast arbiters for on-chip network switches.
Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Galanopoulos
2008Fault tolerant Four-State Logic by using Self-Healing Cells.
Thomas Panhofer, Werner Friesenbichler, Martin Delvai
2008Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA.
Yong Dou, Fei Xia, Xingming Zhou, Xuejun Yang
2008Frequency and voltage planning for multi-core processors under thermal constraints.
Michael Kadin, Sherief Reda
2008Gate planning during placement for gated clock network.
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
2008Global bus route optimization with application to microarchitectural design exploration.
Dae Hyun Kim, Sung Kyu Lim
2008Hierarchical simulation-based verification of Anton, a special-purpose parallel machine.
J. P. Grossman, John K. Salmon, C. Richard Ho, Doug Ierardi, Brian Towles, Brannon Batson, Jochen Spengler, Stanley C. Wang, Rolf Mueller, Michael Theobald, Cliff Young, Joseph Gagliardo, Martin M. Deneroff, Ron O. Dror, David E. Shaw
2008Highly reliable A/D converter using analog voting.
Ali Namazi, Syed Askari, Mehrdad Nourani
2008Improved combined binary/decimal fixed-point multipliers.
Brian J. Hickmann, Michael J. Schulte, Mark A. Erle
2008Improving SAT-based Combinational Equivalence Checking through circuit preprocessing.
Fabrício Vivas Andrade, Leandro Maia Silva, Antônio Otávio Fernandes
2008In-field NoC-based SoC testing with distributed test vector storage.
Jason D. Lee, Rabi N. Mahapatra
2008Is there always performance overhead for regular fabric?
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz
2008Issue system protection mechanisms.
Pedro Chaparro, Jaume Abella, Javier Carretero, Xavier Vera
2008Leveraging speculative architectures for run-time program validation.
Juan Carlos Martínez Santos, Yunsi Fei
2008Low-cost open-page prefetch scheduling in chip multiprocessors.
Marius Grannæs, Magnus Jahre, Lasse Natvig
2008Making register file resistant to power analysis attacks.
Shuo Wang, Fan Zhang, Jianwei Dai, Lei Wang, Zhijie Jerry Shi
2008Mathematical analysis of buffer sizing for Network-on-Chips under multimedia traffic.
Ahmad Khonsari, Mohammad R. Aghajani, Arash Tavakkol, Mohammad Sadegh Talebi
2008Modeling and analysis of non-rectangular transistors caused by lithographic distortions.
Aswin Sreedhar, Sandip Kundu
2008Modeling and reduction of complex timing constraints in high performance digital circuits.
Veerapaneni Nagbhushan, C. Y. Roger Chen
2008Near-optimal oblivious routing on three-dimensional mesh networks.
Rohit Sunkam Ramanujam, Bill Lin
2008On-chip high performance signaling using passive compensation.
Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng
2008Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264.
Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga
2008Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor.
Michael Gschwind
2008Post-silicon verification for cache coherence.
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
2008Power switch characterization for fine-grained dynamic voltage scaling.
Liang Di, Mateja Putic, John C. Lach, Benton H. Calhoun
2008Power-aware soft error hardening via selective voltage scaling.
Kai-Chiang Wu, Diana Marculescu
2008Power-state-aware buffered tree construction.
Iris Hui-Ru Jiang, Ming-Hua Wu
2008Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield.
Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang
2008Probabilistic error propagation in logic circuits using the Boolean difference calculus.
Nasir Mohyuddin, Ehsan Pakbaznia, Massoud Pedram
2008Propositional approximations for bounded model checking of partial circuit designs.
Bernd Becker, Marc Herbstritt, Natalia Kalinnik, Matthew Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer
2008Prototyping a hybrid main memory using a virtual machine monitor.
Dong Ye, Aravind Pavuluri, Carl A. Waldspurger, Brian Tsang, Bohuslav Rychlik, Steven Woo
2008Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads.
Shrirang M. Yardi, Michael S. Hsiao
2008Quantitative global dataflow analysis on virtual instruction set simulators for hardware/software co-design.
Carsten Gremzow
2008RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache.
Hyotaek Shim, Jaegeuk Kim, Dawoon Jung, Jin-Soo Kim, Seungryoul Maeng
2008Re-examining cache replacement policies.
Jason Zebchuk, Srihari Makineni, Donald Newell
2008Reliability-aware Dynamic Voltage Scaling for energy-constrained real-time embedded systems.
Baoxian Zhao, Hakan Aydin, Dakai Zhu
2008Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits.
Feng Shi
2008Reversi: Post-silicon validation system for modern microprocessors.
Ilya Wagner, Valeria Bertacco
2008Ring data location prediction scheme for Non-Uniform Cache Architectures.
Sayaka Akioka, Feihui Li, Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin
2008Router and cell library co-development for improving redundant via insertion at pins.
Wei-Chiu Tseng, Yu-Hsing Chen, Rung-Bin Lin
2008Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW.
Hao Xu, Ranga Vemuri, Wen-Ben Jone
2008Safe clocking register assignment in datapath synthesis.
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2008Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs.
Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Lichun Bao
2008Simulation points for SPEC CPU 2006.
Arun A. Nair, Lizy K. John
2008Suitable cache organizations for a novel biomedical implant processor.
Christos Strydis
2008SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement.
Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi
2008Synthesis of parallel prefix adders considering switching activities.
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
2008Systematic design of high-radix Montgomery multipliers for RSA processors.
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2008Techniques for increasing effective data bandwidth.
Christopher Nitta, Matthew K. Farrens
2008Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlations.
Chunchen Liu, Junjie Su, Yiyu Shi
2008Test cost minimization through adaptive test development.
Mingjing Chen, Alex Orailoglu
2008Test-access mechanism optimization for core-based three-dimensional SOCs.
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie
2008The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks.
Reza Sabbaghi-Nadooshan, Mehdi Modarressi, Hamid Sarbazi-Azad
2008Timing analysis considering IR drop waveforms in power gating designs.
Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2008Two dimensional highly associative level-two cache design.
Chuanjun Zhang, Bing Xue
2008Understanding performance, power and energy behavior in asymmetric multiprocessors.
Nagesh B. Lakshminarayana, Hyesoon Kim
2008Variation-aware thermal characterization and management of multi-core architectures.
Eren Kursun, Chen-Yong Cher
2008ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.
Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum