ICCD C

94 papers

YearTitle / Authors
200725th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings
2007A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS.
Amit Kumar, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha
2007A Study on self-timed asynchronous subthreshold logic.
Niklas Lotze, Maurits Ortmanns, Yiannos Manoli
2007A low overhead hardware technique for software integrity and confidentiality.
Austin Rogers, Milena Milenkovic, Aleksandar Milenkovic
2007A novel O(1) parallel deadlock detection algorithm and architecture for multi-unit resource systems.
Xiang Xiao, Jaehwan John Lee
2007A novel profile-driven technique for simultaneous power and code-size optimization of microcoded IPs.
Bita Gorjiara, Daniel Gajski
2007A parallel IEEE P754 decimal floating-point multiplier.
Brian J. Hickmann, Andrew Krioukov, Michael J. Schulte, Mark A. Erle
2007A position-insensitive finished store buffer.
Erika Gunadi, Mikko H. Lipasti
2007A power gating scheme for ground bounce reduction during mode transition.
Ku He, Rong Luo, Yu Wang
2007A radix-10 SRT divider based on alternative BCD codings.
Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi
2007A technique for selecting CMOS transistor orders.
Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen
2007Accurate modeling and fault simulation of Byzantine resistive bridges.
Hugo Cheung, Sandeep K. Gupta
2007Algorithms to simplify multi-clock/edge timing constraints.
Veerapaneni Nagbhushan, C. Y. Roger Chen
2007Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking.
Philip Jacob, Aamir Zia, Okan Erdogan, Paul M. Belemjian, Peng Jin, Jin Woo Kim, Michael Chu, Russell P. Kraft, John F. McDonald
2007An automated runtime power-gating scheme.
Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki
2007An efficient gate delay model for VLSI design.
Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen
2007An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects.
Jianxun Liu, Wen-Ben Jone
2007Analytical thermal placement for VLSI lifetime improvement and minimum performance variation.
Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu
2007Application of symbolic computer algebra to arithmetic circuit verification.
Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
2007Automatic SystemC TLM generation for custom communication platforms.
Lochi Yu, Samar Abdi
2007Benchmarks and performance analysis of decimal floating-point applications.
Liang-Kai Wang, Charles Tsen, Michael J. Schulte, Divya Jhalani
2007Bounded model checking of embedded software in wireless cognitive radio systems.
Nannan He, Michael S. Hsiao
2007CAP: Criticality analysis for power-efficient speculative multithreading.
James Tuck, Wei Liu, Josep Torrellas
2007CMOS logic design with independent-gate FinFETs.
Anish Muttreja, Niket Agarwal, Niraj K. Jha
2007Cache replacement based on reuse-distance prediction.
Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras
2007Challenges and prospects of SDR for mobile phones.
Ulrich Ramacher
2007Circuit-level mismatch modelling and yield optimization for CMOS analog circuits.
Mingjing Chen, Alex Orailoglu
2007Cluster-level simultaneous multithreading for VLIW processors.
Manoj Gupta, Fermín Sánchez, Josep Llosa
2007Combining cluster sampling with single pass methods for efficient sampling regimen design.
Paul D. Bryan, Thomas M. Conte
2007Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors.
Hai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi
2007Constraint satisfaction in incremental placement with application to performance optimization under power constraints.
Huan Ren, Shantanu Dutt
2007Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine.
Hani Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.
2007Continual hashing for efficient fine-grain state inconsistency detection.
Jae W. Lee, Myron King, Krste Asanovic
2007Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputs.
Siavash Bayat Sarmadi, M. Anwar Hasan
2007Digital calibration of RF transceivers for I-Q imbalances and nonlinearity.
Erkan Acar, Sule Ozev
2007Distributed voting for fault-tolerant nanoscale systems.
Ali Namazi, Mehrdad Nourani
2007Dynamically compressible context architecture for low power coarse-grained reconfigurable array.
Yoonjin Kim, Rabi N. Mahapatra
2007Effective Dynamic Thermal Management for MPEG-4 decoding.
Inchoon Yeo, Heung Ki Lee, Eun Jung Kim, Ki Hwan Yum
2007Energy-aware co-processor selection for embedded processors on FPGAs.
Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Sudarshan Banerjee
2007Evaluating voltage islands in CMPs under process variations.
Abhishek Das, Serkan Ozdemir, Gokhan Memik, Alok N. Choudhary
2007Exploiting eDRAM bandwidth with data prefetching: simulation and measurements.
Valentina Salapura, José R. Brunheroto, Fernando F. Redígolo, Alan Gara
2007Exploring DRAM cache architectures for CMP server platforms.
Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Donald Newell
2007Exploring the interplay of yield, area, and performance in processor caches.
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
2007FPGA global routing architecture optimization using a multicommodity flow approach.
Yuanfang Hu, Yi Zhu, Michael B. Taylor, Chung-Kuan Cheng
2007FPGA routing architecture analysis under variations.
Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan
2007Fast power network analysis with multiple clock domains.
Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng
2007Fault-based alternate test of RF components.
Selim Sermet Akbay, Abhijit Chatterjee
2007Fine grain 3D integration for microarchitecture design through cube packing exploration.
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong
2007Floating-point division algorithms for an x86 microprocessor with a rectangular multiplier.
Michael J. Schulte, Dimitri Tan, Carl Lemonds
2007Hardware design of a Binary Integer Decimal-based floating-point adder.
Charles Tsen, Sonia González-Navarro, Michael J. Schulte
2007Hardware libraries: An architecture for economic acceleration in soft multi-core environments.
David Meisner, Sherief Reda
2007Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits.
Shu Li, Tong Zhang
2007Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.
Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, Chuanjin Richard Shi
2007Improving cache efficiency via resizing + remapping.
Subramanian Ramaswamy, Sudhakar Yalamanchili
2007Improving the reliability of on-chip L2 cache using redundancy.
Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan
2007Improving the reliability of on-chip data caches under process variations.
Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu
2007LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation.
Jugash Chandarlapati, Mainak Chaudhuri
2007Limits on voltage scaling for caches utilizing fault tolerant techniques.
Mohammad A. Makhzan, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi
2007Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor.
Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz
2007Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.
Ming Su, Lili Zhou, Chuanjin Richard Shi
2007Memory based computation using embedded cache for processor yield and reliability improvement.
Somnath Paul, Swarup Bhunia
2007Modeling soft error effects considering process variations.
Chong Zhao, Sujit Dey
2007Multi-core data streaming architecture for ray tracing.
Yoshiyuki Kaeriyama, Daichi Zaitsu, Ken-Ichi Suzuki, Hiroaki Kobayashi, Nobuyuki Ohba
2007Negative-skewed shadow registers for at-speed delay variation characterization.
Jie Li, John C. Lach
2007Non-arithmetic carry chains for reconfigurable fabrics.
Michael T. Frederick, Arun K. Somani
2007On modeling impact of sub-wavelength lithography on transistors.
Aswin Sreedhar, Sandip Kundu
2007Optimized design of a double-precision floating-point multiply-add-dused unit for data dependence.
Gongqiong Li, Zhaolin Li
2007Passive compensation for high performance inter-chip communication.
Chun-Chen Liu, Haikun Zhu, Chung-Kuan Cheng
2007Placement and routing of RF embedded passive designs in LCP substrate.
Mohit Pathak, Souvik Mukherjee, Madhavan Swaminathan, Ege Engin, Sung Kyu Lim
2007Post-layout comparison of high performance 64b static adders in energy-delay space.
Sheng Sun, Carl Sechen
2007Power efficient register file update approach for embedded processors.
Raid Ayoub, Alex Orailoglu
2007Power reduction of chip multi-processors using shared resource control cooperating with DVFS.
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
2007Power variations of multi-port routers in an application-specific NoC design : A case study.
Balasubramanian Sethuraman, Ranga Vemuri
2007Power-aware mapping for reconfigurable NoC architectures.
Mehdi Modarressi, Hamid Sarbazi-Azad
2007Prioritizing verification via value-based correctness criticality.
Joonhyuk Yoo, Manoj Franklin
2007Priority-monotonic energy management for real-time systems with reliability requirements.
Dakai Zhu, Xuan Qi, Hakan Aydin
2007Reducing leakage power in peripheral circuits of L2 caches.
Houman Homayoun, Alexander V. Veidenbaum
2007Register binding guided by the size of variables.
Noureddine Chabini, Wayne H. Wolf
2007SCAFFI: An intrachip FPGA asynchronous interface based on hard macros.
Julian J. H. Pontes, Rafael Soares, Ewerson Carvalho, Fernando Moraes, Ney Calazans
2007Scan chain design for three-dimensional integrated circuits (3D ICs).
Xiaoxia Wu, Paul Falkenstern, Yuan Xie
2007Speed-area optimized FPGA implementation for Full Search Block Matching.
Santosh Ghosh, Avishek Saha
2007Statistical simulation of chip multiprocessors running multi-program workloads.
Davy Genbrugge, Lieven Eeckhout
2007Statistical timing analysis using Kernel smoothing.
Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak
2007System level power estimation methodology with H.264 decoder prediction IP case study.
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt
2007The challenge in testing MIMO in a Wi-Fi or WiMAX context.
Karsten Vandrup
2007Transparent mode flip-flops for collapsible pipelines.
Eric L. Hill, Mikko H. Lipasti
2007Tutorial: Software-defined radio technology.
Mark Cummings, Todor Cooklev
2007Twiddle factor transformation for pipelined FFT processing.
In-Cheol Park, WonHee Son, Ji-Hoon Kim
2007Two-level ata prefetching.
Fei Gao, Hanyu Cui, Suleyman Sair
2007VIZOR: Virtually zero margin adaptive RF for ultra low power wireless communication.
Rajarajan Senguttuvan, Shreyas Sen, Abhijit Chatterjee
2007VOSCH: Voltage scaled cache hierarchies.
Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li
2007Voltage drop reduction for on-chip power delivery considering leakage current variations.
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan
2007Whitespace redistribution for thermal via insertion in 3D stacked ICs.
Eric Wong, Sung Kyu Lim
2007Why we need statistical static timing analysis.
Cristiano Forzan, Davide Pandini