ICCD C

83 papers

YearTitle / Authors
200624th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA
2006A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems.
Chuanjun Zhang
2006A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals.
Kimiyoshi Usami, Naoaki Ohkubo
2006A Low Power Highly Associative Cache for Embedded Systems.
Chuanjun Zhang
2006A New Class of Sequential Circuits with Acyclic Test Generation Complexity.
Chia Yee Ooi, Hideo Fujiwara
2006A Pattern Generation Technique for Maximizing Power Supply Currents.
Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu
2006A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models.
Jinwen Xi, Peixin Zhong
2006A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips.
Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessabi, Hamid Sarbazi-Azad
2006A theory of Error-Rate Testing.
Shideh Shahidi, Sandeep K. Gupta
2006Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug.
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
2006Addressing Multicore Communication Challenges Using NoC Technology.
Drew Wingard
2006An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks.
Sanjay Pant, David T. Blaauw
2006An Efficient, Scalable Hardware Engine for Boolean SATisfiability.
Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi
2006An Enhancement for a Scheduling Logic Pipelined over two Cycles .
Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería
2006An accurate Energy estimation framework for VLIW Processor Cores.
Sourav Roy, Rajat Bhatia, Ashish Mathur
2006Architectural Support for Run-Time Validation of Control Flow Transfer.
Yixin Shi, Sean Dempsey, Gyungho Lee
2006Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths .
Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski
2006Assertion-Based Microarchitecture Design for Improved Reliability.
Vimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi
2006Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD.
Krishnendu Chakrabarty
2006CMOS Comparators for High-Speed and Low-Power Applications.
Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri
2006Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache.
Nathan Sadler, Daniel J. Sorin
2006Clustering-Based Microcode Compression.
Edson Borin, Maurício Breternitz Jr., Youfeng Wu, Guido Araujo
2006Computer Architecture in the Many-Core Era.
William J. Dally
2006Customizable Fault Tolerant Caches for Embedded Processors.
Subramanian Ramaswamy, Sudhakar Yalamanchili
2006Delay and Area Efficient First-level Cache Soft Error Detection and Correction.
Karl Mohr, Lawrence Clark
2006Design Methodology of Regular Logic Bricks for Robust Integrated Circuits.
Kim Yaw Tong, Lawrence T. Pileggi
2006Design and Implementation of Software Objects in Hardware.
Fu-Chiung Cheng, Hung-Chi Wu
2006Design and Implementation of the TRIPS Primary Memory System.
Simha Sethumadhavan, Robert G. McDonald, Rajagopalan Desikan, Doug Burger, Stephen W. Keckler
2006Dynamic Co-Processor Architecture for Software Acceleration on CSoCs.
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar
2006Efficient Testing of RF MIMO Transceivers Used in WLAN Applications.
Erkan Acar, Sule Ozev
2006Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution.
Yi Ma, Huiyang Zhou
2006Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI.
Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy
2006FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.
Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack
2006FPGA Implementation of High Speed FIR Filters Using Add and Shift Method.
Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner
2006FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems.
Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi
2006Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy.
Dan Nicolaescu, Babak Salamat, Alexander V. Veidenbaum
2006Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses.
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
2006Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests.
Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun
2006Guiding Architectural SRAM Models.
Banit Agrawal, Timothy Sherwood
2006High-Level vs. RTL Combinational Equivalence: An Introduction.
Alan Hu
2006High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding.
Xinmiao Zhang
2006Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja
2006Implementation and Evaluation of On-Chip Network Architectures.
Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger
2006Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles.
Zhiyi Yu, Bevan M. Baas
2006Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique.
Kameshwar Chandrasekar, Michael S. Hsiao
2006Improving Power and Data Efficiency with Threaded Memory Modules.
Frederick A. Ware, Craig Hampel
2006Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling.
Kuo-Su Hsiao, Chung-Ho Chen
2006Interconnect Considerations For High Performance Network on Chip Designs.
Uri Cummings
2006Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction.
Rasit Onur Topaloglu, Andrew B. Kahng
2006Iterative-Constructive Standard Cell Placer for High Speed and Low Power.
Sungjae Kim, Eugene Shragowitz
2006Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing.
Shuo Wang, Lei Wang
2006Long-term Performance Bottleneck Analysis and Prediction.
Fei Gao, Suleyman Sair
2006Microarchitecture and Performance Analysis of Godson-2 SMT Processor.
Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang
2006On the Improvement of Statistical Static Timing Analysis.
Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri
2006Partial Functional Manipulation Based Wirelength Minimization.
Avijit Dutta, David Z. Pan
2006Patching Processor Design Errors.
Satish Narayanasamy, Bruce Carneal, Brad Calder
2006Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors.
Sean Leventhal, Manoj Franklin
2006Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection.
Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Saurabh Bagchi
2006Polaris: A System-Level Roadmap for On-Chip Interconnection Networks.
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh
2006Power Droop Testing.
Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker
2006Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
2006Power/ground supply network optimization for power-gating.
Hailin Jiang, Malgorzata Marek-Sadowska
2006Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects.
Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye
2006RTL Scan Design for Skewed-Load At-speed Test under Power Constraints.
Ho Fai Ko, Nicola Nicolici
2006RasP: An Area-efficient, On-chip Network.
Simon Hollis, Simon W. Moore
2006Reconfigurable CAM Architecture for Network Search Engines.
Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara
2006Reduce Register Files Leakage Through Discharging Cells.
Lingling Jin, Wei Wu, Jun Yang, Chuanjun Zhang, Youtao Zhang
2006Reduction of Crosstalk Pessimism using Tendency Graph Approach.
Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier
2006Reliability Support for On-Chip Memories Using Networks-on-Chip.
Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli
2006Requirements and Concepts for Transaction Level Assertions.
Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten
2006Scalable Sequential Equivalence Checking across Arbitrary Design Transformations .
Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman, Geert Janssen
2006Scale in Chip Interconnect requires Network Technology .
Enno Wein
2006Scaling Manufacturability Software to Thousands of Processors.
Fabio Angelillis
2006Seqver : A Sequential Equivalence Verifier for Hardware Designs .
Daher Kaiss, Silvian Goldenberg, Zurab Khasidashvili
2006Simulation-based functional test justification using a decision-digram-based Boolean data miner.
Charles H.-P. Wen, Onur Guzey, Li-C. Wang
2006Speculative Code Value Specialization Using the Trace Cache Fill Unit.
Weifeng Zhang, Brad Calder, Dean M. Tullsen, Steve Checkoway
2006Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture.
Tinoosh Mohsenin, Bevan M. Baas
2006Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation.
Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan
2006Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates.
Saraju P. Mohanty, Elias Kougianos
2006Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach.
Hwisung Jung, Massoud Pedram
2006System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors.
Xiaofang Wang, Sotirios G. Ziavras
2006Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems.
Shaobo Liu, Qinru Qiu, Qing Wu
2006Trends and Future Directions in Nano Structure Based Computing and Fabrication.
R. Iris Bahar