ICCD C

117 papers

YearTitle / Authors
200523rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA
2005A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits.
Valmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos
2005A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.
Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De
2005A Feasibility Study of Subthreshold SRAM Across Technology Generations.
Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
2005A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs.
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
2005A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management.
Shrirang M. Yardi, Karthik Channakeshava, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha
2005A High Performance Sub-Pipelined Architecture for AES.
Hua Li, Jianzhou Li
2005A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction.
Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi
2005A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation.
Marco Antonio Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa
2005A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.
Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
2005A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.
Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
2005A Soft Error Monitor Using Switching Current Detection.
Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy
2005A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs.
Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
2005A Waveform Independent Gate Model for Accurate Timing Analysis.
Peng Li, Emrah Acar
2005ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology.
Wei Zhang, Niraj K. Jha
2005Accurate Diagnosis of Multiple Faults.
Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
2005Additional Reviewers.
2005Algorithmic and Architectural Design Methodology for Particle Filters in Hardware.
Aswin C. Sankaranarayanan, Rama Chellappa, Ankur Srivastava
2005An Improved Approach for AlternativeWires Identi.cation.
Yung-Chih Chen, Chun-Yao Wang
2005Analytical Model for Sensor Placement on Microprocessors.
Kyeong-Jae Lee, Kevin Skadron, Wei Huang
2005Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms.
Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini
2005Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation.
Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler
2005Architectural Considerations for Energy Efficiency.
Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
2005Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors.
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2005Are Today's Verification Tools Able to Handle Current Design Challenges?
Rich Faris, Ken Larsen, Harry Foster, Stuart Swan
2005Assertion Checking of Behavioral Descriptions with Non-linear Solver.
Íñigo Ugarte, Pablo Sanchez
2005Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow.
Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton
2005At-Speed Logic BIST Architecture for Multi-Clock Designs.
Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo
2005Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance.
Luis A. Plana, Sam Taylor, Doug A. Edwards
2005Automatic Synthesis of Composable Sequential Quantum Boolean Circuits.
Li-Kai Chang, Fu-Chiung Cheng
2005Benefits and Costs of Power-Gating Technique.
Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif
2005Broadband Impedance Matching for Inductive Interconnect in VLSI Packages.
Brock J. LaMeres, Sunil P. Khatri
2005Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core.
Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham
2005Challenges in the Formal Verification of Complete State-of-the-Art Processors.
Nathaniel Ayewah, Nikhil Kikkeri, Peter-Michael Seidel
2005ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values.
Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
2005Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree.
Gang Zeng, Hideo Ito
2005Copyright.
2005Correlation between Detailed and Simplified Simulations in Studying Multiprocessor Architecture.
Khaled Z. Ibrahim
2005Counter-Based Cache Replacement Algorithms.
Mazen Kharbutli, Yan Solihin
2005Dealing with I/O Devices in the Context of Pervasive System Verification.
Mark A. Hillebrand, Thomas In der Rieden, Wolfgang J. Paul
2005Deployment of Better Than Worst-Case Design: Solutions and Needs.
Todd M. Austin, Valeria Bertacco
2005Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study.
Soheil Ghiasi
2005Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages.
Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li
2005Efficient Thermal Simulation for Run-Time Temperature Tracking and Management.
Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang
2005Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System.
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede
2005Energy-Efficient Color Approximation for Digital LCD Interfaces.
Andi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino
2005Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis.
Fei Hu, Vishwani D. Agrawal
2005Error-tolerance memory Microarchitecture via Dynamic Multithreading.
Lei Wang
2005Exact lower bound for the number of switches in series to implement a combinational logic cell.
Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
2005Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths.
Namrata Shekhar, Priyank Kalla, Sivaram Gopalakrishnan, Florian Enescu
2005Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults.
Manan Syal, Rajat Arora, Michael S. Hsiao
2005FRAM Memory Technology - Advantages for Low Power, Fast Write, High Endurance Applications.
Rick Bailey, Glen Fox, Jarrod Eliason, Marty Depner, Daesig Kim, Edwin Jabillo, John Groat, John Walbert, Scott R. Summerfelt, K. R. Udayakumar, John Rodriquez, Keith Remack, K. Boku, John Gertas
2005Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits.
Fang Liu, Sule Ozev
2005Fast Minimum and Maximum Selection.
Anatoly I. Grushin
2005Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration.
Song Peng, Rajit Manohar
2005File System Interfaces for Embedded Software Development.
Bhanu Pisupati, Geoffrey Brown
2005Formal Verification and its Impact on the Snooping versus Directory Protocol Debate.
Milo M. K. Martin
2005Formal Verification of Parametric Multiplicative Division Implementations.
Nikhil Kikkeri, Peter-Michael Seidel
2005Frame Buffer Energy Optimization by Pixel Prediction.
Kimish Patel, Enrico Macii, Massimo Poncino
2005H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication.
Xizhen Xu, Sotirios G. Ziavras
2005Hardware Ef.cient LBISTWith Complementary Weights.
Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
2005Hardware Support for Bulk Data Movement in Server Platforms.
Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan, Donald Newell
2005Implementing Caches in a 3D Technology for High Performance Processors.
Kiran Puttaswamy, Gabriel H. Loh
2005Incorporating Ef.cient Assertion Checkers into Hardware Emulation.
Marc Boule, Zeljko Zilic
2005LCD Display Energy Reduction by User Monitoring.
Vasily G. Moshnyaga, Eiji Morikawa
2005Latency Lags Bandwidth.
David A. Patterson
2005Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners.
Anuradha Agarwal, Ranga Vemuri
2005Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism..
Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
2005Low- and Ultra Low-Power Arithmetic Units: Design and Comparison.
Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija
2005Low-Power Design of 90-nm SuperH Processor Core.
Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori
2005Memory Bank Predictors.
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González
2005Methods for Modeling Resource Contention on Simultaneous Multithreading Processors.
Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Daniel A. Connors
2005Minimum Energy Near-threshold Network of PLA based Design.
Nikhil Jayakumar, Sunil P. Khatri
2005Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag.
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
2005Model Checking C Programs Using F-SOFT.
Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai, Vineet Kahlon, Chao Wang, Zijiang Yang
2005Monitoring Temperature in FPGA based SoCs.
Sivakumar Velusamy, Wei Huang, John C. Lach, Mircea R. Stan, Kevin Skadron
2005Near-memory Caching for Improved Energy Consumption.
Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem
2005Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
2005Optimizing the Thermal Behavior of Subarrayed Data Caches.
Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
2005Organizing Committee.
2005Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm.
Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa
2005Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz.
Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng
2005Power-Efficient Wakeup Tag Broadcast.
Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin
2005Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement.
Qinghua Liu, Malgorzata Marek-Sadowska
2005Program Committee.
2005Quality Transition Fault Tests Suitable for Small Delay Defects.
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas
2005Quick Scan Chain Diagnosis Using Signal Profiling.
Jheng-Syun Yang, Shi-Yu Huang
2005RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free".
Won-Ho Park, Andreas Moshovos, Babak Falsafi
2005Reconsidering CEGAR: Learning Good Abstractions without Refinement.
Anubhav Gupta, Edmund M. Clarke
2005Reducing the Energy of Speculative Instruction Schedulers.
Yongxiang Liu, Gokhan Memik, Glenn Reinman
2005Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines.
Anahita Shayesteh, Eren Kursun, Timothy Sherwood, Suleyman Sair, Glenn Reinman
2005Restrictive Compression Techniques to Increase Level 1 Cache Capacity.
Prateek Pujara, Aneesh Aggarwal
2005Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines.
Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara
2005Robust Design of High Fan-In/Out Subthreshold Circuits.
Jinhui Chen, Lawrence T. Clark, Yu Cao
2005SST: Symbolic Subordinate Threading.
Rania H. Mameesh, Manoj Franklin
2005Simulating Commercial Java Throughput Workloads: A Case Study.
Yue Luo, Lizy Kurian John
2005State Set Management for SAT-based Unbounded Model Checking.
Kameshwar Chandrasekar, Michael S. Hsiao
2005Statistical Analysis Driven Synthesis of Asynchronous Systems.
Koji Ohashi, Mineo Kaneko
2005Supply Voltage Degradation Aware Analytical Placement.
Andrew B. Kahng, Bao Liu, Qinke Wang
2005Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications.
Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris
2005Temperature-Aware Voltage Islands Architecting in System-on-Chip Design.
Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner
2005Temperature-Dependent Optimization of Cache Leakage Power Dissipation.
Peng Li, Yangdong Deng, Lawrence T. Pileggi
2005Temperature-Sensitive Loop Parallelization for Chip Multiprocessors.
Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie
2005Temporal Decomposition for Logic Optimization.
Nathan Kitchen, Andreas Kuehlmann
2005The TM3270 Media-Processor Data Cache.
Jan-Willem van de Waerdt, Stamatis Vassiliadis, Jean-Paul van Itegem, Hans Van Antwerpen
2005Three-Dimensional Cache Design Exploration Using 3DCacti.
Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2005Title Page.
2005Towards finding path delay fault tests with high test efficiency using ZBDDs.
Maria K. Michael, Kyriakos Christou, Spyros Tragoudas
2005Towards the Formal Verification of Lower System Layers in Automotive Systems.
Sven Beyer, Peter Böhm, Michael Gerke, Mark A. Hillebrand, Thomas In der Rieden, Steffen Knapp, Dirk Leinenbach, Wolfgang J. Paul
2005Using Scratchpad to Exploit Object Locality in Java.
Carl S. Lebsack, J. Morris Chang
2005Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.
Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski
2005VALVE: Variable Length Value Encoder for Off-Chip Data Buses..
Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang
2005VGTA: Variation Aware Gate Timing Analysis.
Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
2005Variability-Driven Buffer Insertion Considering Correlations.
Azadeh Davoodi, Ankur Srivastava
2005Welcome Message.
2005X-Routing using Two Manhattan Route Instances.
Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra
2005Yesterday and Tomorrow: A View on Progress in Computer Design.
Michael J. Flynn