ICCD C

91 papers

YearTitle / Authors
200422nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings
20043D Processing Technology and Its Impact on iA32 Microprocessors.
Bryan Black, Donald Nelson, Clair Webb, Nick Samra
2004A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits.
Hasan Arslan, Shantanu Dutt
2004A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan
2004A Flexible Data Structure for Efficient Buffer Insertion.
Ruiming Chen, Hai Zhou
2004A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs.
John C. Lach, Jason Brandon, Kevin Skadron
2004A High-Frequency Decimal Multiplier.
Robert D. Kenney, Michael J. Schulte, Mark A. Erle
2004A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits.
Srivathsan Krishnamohan, Nihar R. Mahapatra
2004A Minimal Dual-Core Speculative Multi-Threading Architecture.
Srikanth T. Srinivasan, Haitham Akkary, Tom Holman, Konrad Lai
2004A New Statistical Optimization Algorithm for Gate Sizing.
Murari Mani, Michael Orshansky
2004A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters.
Saumil Shah, Kanak Agarwal, Dennis Sylvester
2004A Novel Low-Power Scan Design Technique Using Supply Gating.
Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
2004A Signal Integrity Test Bed for PCB Buses.
Jihong Ren, Mark R. Greenstreet
2004A Two-Layer Bus Routing Algorithm for High-Speed Boards.
Muhammet Mustafa Ozdal, Martin D. F. Wong
2004ACG-Adjacent Constraint Graph for General Floorplans.
Hai Zhou, Jia Wang
2004Adaptive Selection of an Index in a Texture Cache.
Chun-Ho Kim, Lee-Sup Kim
2004An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems.
Hashem Hashemi Najaf-abadi, Hamid Sarbazi-Azad
2004An Architectural Power Estimator for Analog-to-Digital Converters.
Zhaohui Huang, Peixin Zhong
2004An Architecture for Fast Processing of Large Unstructured Data Sets.
Mark A. Franklin, Roger D. Chamberlain, Michael Henrichs, E. F. Berkley Shands, Jason White
2004An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices.
Justin Hensley, Anselmo Lastra, Montek Singh
2004An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks.
Pallav Gupta, Rui Zhang, Niraj K. Jha
2004An Efficient Algorithm for Reconfiguring Shared Spare RRAM.
Hung-Yau Lin, Hong-Zu Chou, Fu-Min Yeh, Ing-Yi Chen, Sy-Yen Kuo
2004An Efficient Twin-Precision Multiplier.
Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
2004An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing.
Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li
2004An Infrastructure IP for On-Chip Clock Jitter Measurement.
Jui-Jer Huang, Jiun-Lang Huang
2004Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor.
Mirko Loghi, Luca Benini, Massimo Poncino
2004Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses.
Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag
2004Asynchronous Scan-Latch controller for Low Area Overhead DFT.
Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
2004Best of Both Latency and Throughput.
Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang
2004Cache Array Architecture Optimization at Deep Submicron Technologies.
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann
2004Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation.
Donald Chai, Andreas Kuehlmann
2004Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field.
Hu Huang, Joseph B. Bernstein, Martin Peckerar, Ji Luo
2004Comparative Study of Strategies for Formal Verification of High-Level Processors.
Miroslav N. Velev
2004Compiler-Based Frame Formation for Static Optimization.
Feng Shi, Sobeeh Almukhaizim, Pey-Chang Lin, Yiorgos Makris
2004Compressed Embedded Diagnosis of Logic Cores.
Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici
2004Coping with The Variability of Combinational Logic Delays.
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou
2004Defining Wakeup Width for Efficient Dynamic Scheduling.
Aneesh Aggarwal, Manoj Franklin, Oguz Ergin
2004Design Methodologies and Architecture Solutions for High-Performance Interconnects.
Davide Pandini, Cristiano Forzan, Livio Baldi
2004Design and Implementation of Scalable Low-Power Montgomery Multiplier.
Hee-Kwan Son, Sang-Geun Oh
2004Design-Space Exploration of Power-Aware On/Off Interconnection Networks.
Vassos Soteriou, Li-Shiuan Peh
2004Diagnosis of Hold Time Defects.
Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2004Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study.
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
2004End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths.
Sule Ozev, Alex Orailoglu
2004Energy Characterization of Hardware-Based Data Prefetching.
Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
2004Evaluating Techniques for Exploiting Instruction Slack.
Yau Chin, John Sheu, David M. Brooks
2004Exploiting Quiescent States in Register Lifetime.
Rama Sangireddy, Arun K. Somani
2004Extending the Applicability of Parallel-Serial Scan Designs.
Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu
2004FPGA Emulation of Quantum Circuits.
Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka
2004Fetch Halting on Critical Load Misses.
Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss
2004Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking.
Chao Wang, Gary D. Hachtel, Fabio Somenzi
2004Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed.
Dongku Kang, Hunsoo Choo, Kaushik Roy
2004Formal Hardware Verification based on Signal Correlation Properties.
Nikhil Kikkeri, Peter-Michael Seidel
2004Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2.
Grigorios Magklis, José González, Antonio González
2004Functional Illinois Scan Design at RTL.
Ho Fai Ko, Nicola Nicolici
2004Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction.
Feng Gao, John P. Hayes
2004Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs.
Kelvin Ng, Alan J. Hu, Jin Yang
2004Graph Automorphism-Based Algorithm for Determining Symmetric Inputs.
Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou
2004Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC.
Jinwen Xi, Peixin Zhong
2004I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
2004IPC Driven Dynamic Associative Cache Architecture for Low Energy.
Sriram Nadathur, Akhilesh Tyagi
2004Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling.
Joshua L. Kihm, Daniel A. Connors
2004In-System FPGA Prototyping of an Itanium Microarchitecture.
Roland E. Wunderlich, James C. Hoe
2004Increasing Processor Performance Through Early Register Release.
Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose
2004Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning.
Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
2004Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures.
Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
2004Low Energy, Highly-Associative Cache Design for Embedded Processors.
Alexander V. Veidenbaum, Dan Nicolaescu
2004Low Power Test Data Compression Based on LFSR Reseeding.
Jinkyu Lee, Nur A. Touba
2004Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures.
Chan-Eun Rhee, Han-You Jeong, Soonhoi Ha
2004Network-on-Chip: The Intelligence is in The Wire.
Gérard Mas, Philippe Martin
2004On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan.
Irith Pomeranz, Sudhakar M. Reddy
2004On-Chip Transparent Wire Pipelining.
Mario R. Casu, Luca Macchiarulo
2004PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks.
Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara
2004Placement with Alignment and Performance Constraints Using the B*-Tree Representation.
Meng-Chen Wu, Yao-Wen Chang
2004Potential Slack Budgeting with Clock Skew Optimization.
Kai Wang, Malgorzata Marek-Sadowska
2004Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure.
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim
2004Quality Improvement Methods for System-Level Stimuli Generation.
Roy Emek, Itai Jaeger, Yoav Katz, Yehuda Naveh
2004Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm.
Yu Bai, R. Iris Bahar
2004Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers.
Martin D. F. Wong
2004Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution.
A. Murat Fiskiran, Ruby B. Lee
2004Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems.
Madhubanti Mukherjee, Ranga Vemuri
2004Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing.
Tianpei Zhang, Sachin S. Sapatnekar
2004Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures.
Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino
2004Static Transition Probability Analysis Under Uncertainty.
Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam
2004Technique to Eliminate Sorting in IP Packet Forwarding Devices.
Raymond W. Baldwin, Enrico Ng
2004The Magic of a Via-Configurable Regular Fabric.
Yajun Ran, Malgorzata Marek-Sadowska
2004Thermal-Aware Clustered Microarchitectures.
Pedro Chaparro, José González, Antonio González
2004Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture.
Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
2004Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems.
Radu Marculescu, Diana Marculescu, Larry T. Pileggi
2004Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits.
Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
2004Using Circuits and Systems-Level Research to Drive Nanotechnology.
Michael T. Niemier, Ramprasad Ravichandran, Peter M. Kogge
2004XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs.
Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma