ICCD C

89 papers

YearTitle / Authors
200119th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings
20013DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis.
Hiroaki Kobayashi, Ken-Ichi Suzuki, Kentaro Sano, Yoshiyuki Kaeriyama, Yasumasa Saida, Nobuyuki Oba, Tadao Nakamura
2001A Banked-Promotion TLB for High Performance and Low Power.
Jung-Hoon Lee, Jang-Soo Lee, Seh-Woong Jeong, Shin-Dug Kim
2001A Framework for Energy Estimation of VLIW Architecture.
Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2001A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage.
Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer
2001A Heuristic for Multiple Weight Set Generation.
Hong-Sik Kim, Jin-kyue Lee, Sungho Kang
2001A Hierarchical Dependence Check and Folded Rename Mapping Based Scalable Dispatch Stage.
Vadhiraj Sankaranarayanan, Akhilesh Tyagi
2001A Low-Power Cache Design for CalmRISC
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong
2001A New Functional Test Program Generation Methodology.
Farzan Fallah, Koichiro Takayama
2001A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits.
Irith Pomeranz, Sudhakar M. Reddy
2001A Performance Analysis of the Active Memory System.
Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang
2001A Single-Multiplier Quadratic Interpolator for LNS Arithmetic.
Mark G. Arnold, Mark D. Winkel
2001A Timing-Driven Macro-Cell Placement Algorithm.
Fan Mo, Abdallah Tabbara, Robert K. Brayton
2001Access Region Cache: A Multi-Porting Solution for Future Wide-Issue Processors.
Bhooshan S. Thakar, Gyungho Lee
2001Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme.
Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson
2001Alloyed Path-pattern Scheme for Branch Prediction.
Rajesh Ramanujam, Murali Ravirala, Gyungho Lee
2001An Algorithm for Dynamically Reconfigurable FPGA Placement.
Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
2001An Analytical Model for Trace Cache Instruction Fetch Performance.
Afzal Hossain, Daniel J. Pease
2001An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking.
Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park
2001Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits.
Payam Heydari, Massoud Pedram
2001Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications.
John Patrick McGregor, Ruby B. Lee
2001Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation.
Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
2001Arithmetic Transforms for Verifying Compositions of Sequential Datapaths.
Katarzyna Radecka, Zeljko Zilic
2001Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors.
Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar
2001BDD Variable Ordering by Scatter Search.
William N. N. Hung, Xiaoyu Song
2001Buffered Interconnect Tree Optimization Using Lagrangian Relaxation and Dynamic Programming.
Shih-Yih Lai, Ross Baldick
2001COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction.
Irith Pomeranz, Sudhakar M. Reddy
2001Clear and Present Tensions in Microprocessor Design.
John Paul Shen
2001Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation.
Kent E. Wires, Michael J. Schulte, James E. Stine
2001Compiler-Directed Classification of Value Locality Behavior.
Qing Zhao, David J. Lilja
2001Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement.
Dong Xiang, Yi Xu
2001Cost-effective Hardware Acceleration of Multimedia Applications.
Deependra Talla, Lizy Kurian John
2001Crosstalk Noise Estimation for Generic RC Trees.
Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera
2001Design Alternatives for Parallel Saturating Multioperand Adders.
Pablo I. Balzola, Michael J. Schulte, Jie Ruan, C. John Glossner, Erdem Hokenek
2001Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures.
Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
2001Designing Circuits for Disk Drives.
Georg Pelz
2001Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages.
Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria
2001Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits.
Dragos Lungeanu, Chuanjin Richard Shi
2001Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification Problem.
Jennifer L. White, Moon-Jung Chung, Anthony S. Wojcik, Travis E. Doom
2001Efficient Function Approximation for Embedded and ASIC Applications.
James W. Hauser, Carla Neaderhouser Purdy
2001Efficient Systematic Error-correcting Codes for Semi-Delay-Insensitive Data Transmission.
Fu-Chiung Cheng, Shuen-Long Ho
2001Fast Specification of Cycle-accurate Processor Models.
Felix Sheng-Ho Chang, Alan J. Hu
2001Filtering Superfluous Prefetches Using Density Vectors.
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger, Thomas R. Puzak
2001Fixed-outline Floorplanning through Better Local Search.
Saurabh N. Adya, Igor L. Markov
2001Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement.
Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh
2001Gate Sizing to Eliminate Crosstalk Induced Timing Violation.
Tong Xiao, Malgorzata Marek-Sadowska
2001Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.
Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang
2001Hard Disk Controller: The Disk Drive's Brain and Body.
James Jeppensen, Walt Allen, Steve Anderson, Michael Pilsl
2001Hierarchical Image Computation with Dynamic Conjunction Scheduling.
Christoph Meinel, Christian Stangier
2001High Performance Parallel Fault Simulation.
Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller
2001High-Level Power Modeling of CPLDs and FPGAs.
Li Shang, Niraj K. Jha
2001Improved ZDN-arithmetic for Fast Modulo Multiplication.
Hagen Ploog, Sebastian Flügel, Dirk Timmermann
2001In-Line Interrupt Handling for Software-Managed TLBs.
Aamer Jaleel, Bruce L. Jacob
2001Interconnect-centric Array Architectures for Minimum SRAM Access Time.
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl
2001Introduction to Generalized Symbolic Trajectory Evaluation.
Jin Yang, Carl-Johan H. Seger
2001Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective.
Payam Heydari, Massoud Pedram
2001Linear Time Hierarchical Capacitance Extraction without Multipole Expansion.
Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, Charlie Chung-Ping Chen
2001Low-Energy DSP Code Generation Using a Genetic Algorithm.
Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard P. Fettweis
2001Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis.
Alicia Manthe, Chuanjin Richard Shi
2001MCOMA: A Multithreaded COMA Architecture.
Halima El Naga, Jean-Luc Gaudiot
2001MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines.
Montek Singh, Steven M. Nowick
2001MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor.
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
2001Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem.
Ying Zhao, Sharad Malik, Albert R. Wang, Matthew W. Moskewicz, Conor F. Madigan
2001Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State.
John W. Haskins Jr., Kevin Skadron
2001Moore's Law Meets Shannon's Law: The Evolution of the Communication's Industry.
Lee M. Harrison
2001Motion-Control: The Power Side of Disk Drives.
Wolfgang Sereinig
2001Mutable Functional Units and Their Applications on Microprocessors.
Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya B. Gokhale
2001On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs.
Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl
2001On-Chip Oscilloscopes for Noninvasive Time-domain Measurement of Waveforms.
Kenneth L. Shepard, Yu Zheng
2001On-Line Integrity Monitoring of Microprocessor Control Logic.
Seongwoo Kim, Arun K. Somani
2001Parallel Cachelets.
Deepak Limaye, Ryan N. Rakvic, John Paul Shen
2001Performance Driven Global Routing Through Gradual Refinement.
Jiang Hu, Sachin S. Sapatnekar
2001Performance Impact of Addressing Modes on Encryption Algorithms.
A. Murat Fiskiran, Ruby B. Lee
2001Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model.
Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
2001Pre-routing Estimation of Shielding for RLC Signal Integrity.
James D. Z. Ma, Arvind Parihar, Lei He
2001RC-in RC-out Model Order Reduction Accurate up to Second Order Moments.
Pradeepsunder Ganesh, Charlie Chung-Ping Chen
2001Realization of Multiple-Output Functions by Reconfigurable Cascades.
Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
2001Reducing Cache Pollution of Prefetching in a Small Data Cache.
Pipat Reungsang, Sun Kyu Park, Seh-Woong Jeong, Hyung-Lae Roh, Gyungho Lee
2001Run-Time Execution of Reconfigurable Hardware in a Java Environment.
Laurie A. Smith King, Heather Quinn, Miriam Leeser, Demetris G. Galatopoullos, Elias S. Manolakos
2001Selecting A Well Distributed Hard Case Test Suite for IEEE Standard Floating Point Division.
Lee D. McFearin, David W. Matula
2001Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow.
Juan L. Aragón, José González, José M. García, Antonio González
2001Static Energy Reduction Techniques for Microprocessor Caches.
Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger
2001Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores.
Qianrong Ma, Jih-Kwon Peir, Lu Peng, Konrad Lai
2001The In-Car Computing Network: An Embedded Systems Challenge.
Karl-Thomas Neumann
2001Timing Characterization of Dual-edge Triggered Flip-flops.
Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
2001Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems.
Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
2001Use of Local Memory for Efficient Java Execution.
Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2001Voltage Scaling for Energy Minimization with QoS Constraints.
Ali Manzak, Chaitali Chakrabarti
2001towards A formal Model of Shared Memory Consistency for Intel Itanium
Prosenjit Chatterjee, Ganesh Gopalakrishnan