| 2000 | A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages. Yul Chu, Mabo Robert Ito |
| 2000 | A Decompression Architecture for Low Power Embedded Systems. Haris Lekatsas, Jörg Henkel, Wayne H. Wolf |
| 2000 | A Direct Mapping FPGA Architecture for Industrial Process Control Applications. John T. Welch, Joan Carletta |
| 2000 | A Methodology and Tool for Automated Transformational High-Level Design Space Exploration. Joachim Gerlach, Wolfgang Rosenstiel |
| 2000 | A Multi-Level Memory System Architecture for High-Performance DSP Applications. Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley |
| 2000 | A Novel Low-Power Microprocessor Architecture. Rolf Hakenes, Yiannos Manoli |
| 2000 | A Power Perspective of Value Speculation for Superscalar Microprocessors. Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado |
| 2000 | A Register File with Transposed Access Mode. Yoochang Jung, Stefan G. Berg, Donglok Kim, Yongmin Kim |
| 2000 | A Scalable High-Performance DMA Architecture for DSP Applications. Dave Comisky, Sanjive Agarwala, Charles Fuoco |
| 2000 | A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval. Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim |
| 2000 | A Study of Channeled DRAM Memory Architectures. Lars Friebe, Yoshikazu Yabe, Masato Motomura |
| 2000 | A Technique for Identifying RTL and Gate-Level Correspondences. Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana |
| 2000 | A Trace Based Evaluation of Speculative Branch Decoupling. Anshuman S. Nadkarni, Akhilesh Tyagi |
| 2000 | AMULET3: A 100 MIPS Asynchronous Embedded Processor. Stephen B. Furber, David A. Edwards, Jim D. Garside |
| 2000 | Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond. Toru Hiyama, Yuko Ito, Satoru Isomura, Kazunobu Nojiri, Eijiro Maeda |
| 2000 | An Adder Using Charge Sharing and its Application in DRAMs. Hak-Soo Yu, Songjun Lee, Jacob A. Abraham |
| 2000 | An Advanced Instruction Folding Mechanism for a Stackless Java Processor. Austin Kim, J. Morris Chang |
| 2000 | An Application of Genetic Algorithms and BDDs to Functional Testing. Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi |
| 2000 | An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design. Michael Cogswell, Don Pearl, James Sage, Alan Troidl |
| 2000 | An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines Theory. Nasser Masoumi, Safieddin Safavi-Naeini, Mohamed I. Elmasry |
| 2000 | An Evaluation of Move-Based Multi-Way Partitioning Algorithms. Elie Yarack, Joan Carletta |
| 2000 | An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications. Alfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani |
| 2000 | Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping. Junwei Hou, Abhijit Chatterjee |
| 2000 | Analysis and Optimization of Ground Bounce in Digital CMOS Circuits. Payam Heydari, Massoud Pedram |
| 2000 | Analysis of Shared Memory Misses and Reference Patterns. Jeffrey B. Rothman, Alan Jay Smith |
| 2000 | Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPC Yi-Kan Cheng, David Bearden, Kanti Suryadevara |
| 2000 | Architectural Impact of Secure Socket Layer on Internet Servers. Krishna Kant, Ravishankar K. Iyer, Prasant Mohapatra |
| 2000 | Architectural Support for Dynamic Memory Management. J. Morris Chang, Witawas Srisa-an, Chia-Tien Dan Lo |
| 2000 | Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis. Koji Ohashi, Mineo Kaneko, Satoshi Tayu |
| 2000 | Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 2000 | Buffer Library Selection. José Luis Neves, Stephen T. Quay |
| 2000 | Cheap Out-of-Order Execution Using Delayed Issue. J. P. Grossman |
| 2000 | Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors. Yanhong Yuan, Prithviraj Banerjee |
| 2000 | Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. Song-Ra Pan, Yao-Wen Chang |
| 2000 | Current-Mode Threshold Logic Gates. Sudhakar Bobba, Ibrahim N. Hajj |
| 2000 | DRAM-Page Based Prediction and Prefetching. Haifeng Yu, Gershon Kedem |
| 2000 | Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. I-Min Liu, Adnan Aziz |
| 2000 | Design of Instruction Stream Buffer with Trace Support for X86 Processors. Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung |
| 2000 | Dynamic Flip-Flop with Improved Power. Nikola Nedovic, Vojin G. Oklobdzija |
| 2000 | Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors. Tim Anderson, Sanjive Agarwala |
| 2000 | Efficient Design Error Correction of Digital Circuits. Dirk W. Hoffmann, Thomas Kropf |
| 2000 | Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. Wolfgang Günther, Rolf Drechsler, Stefan Höreth |
| 2000 | Efficient Logic Optimization Using Regularity Extraction. Thomas Kutzschebauch |
| 2000 | Efficient Place and Route for Pipeline Reconfigurable Architectures. Srihari Cadambi, Seth Copen Goldstein |
| 2000 | Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation. Viresh Paruthi, Andreas Kuehlmann |
| 2000 | Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |
| 2000 | Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures. Deependra Talla, Lizy Kurian John, Viktor S. Lapinskii, Brian L. Evans |
| 2000 | Fast Hierarchical Floorplanning with Congestion and Timing Control. Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh |
| 2000 | Fast Subword Permutation Instructions Using Omega and Flip Network Stages. Xiao Yang, Ruby B. Lee |
| 2000 | Fixed-Width Multiplier for DSP Application. Shyh-Jye Jou, Hui-Hsuan Wang |
| 2000 | Formal Verification of an Industrial System-on-a-Chip. Hoon Choi, Myung-Kyoon Yim, Jae Young Lee, Byeong-Whee Yun, Yun-Tae Lee |
| 2000 | Hierarchical Simulation of a Multiprocessor Architecture. Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra |
| 2000 | High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. Naran Sirisantana, Liqiong Wei, Kaushik Roy |
| 2000 | High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang |
| 2000 | Hybridizing and Coalescing Load Value Predictors. Martin Burtscher, Benjamin G. Zorn |
| 2000 | Interfacing Hardware and Software Using C++ Class Libraries. Dinesh Ramanathan, Rajesh K. Gupta, Raymond Roth |
| 2000 | Leakage Power Analysis and Reduction during Behavioral Synthesis. Kamal S. Khouri, Niraj K. Jha |
| 2000 | Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications. Wael M. Badawy, Magdy A. Bayoumi |
| 2000 | Minimization of Ordered Pseudo Kronecker Decision Diagrams. Per Lindgren, Rolf Drechsler, Bernd Becker |
| 2000 | Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification. Fabiano Hessel, Philippe Coste, Gabriela Nicolescu, P. LeMarrec, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya |
| 2000 | Multilevel Reverse-Carry Adder. Javier D. Bruguera, Tomás Lang |
| 2000 | On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs. Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari |
| 2000 | On Multiple Precision Based Montgomery Multiplication without Precomputation of N0´ = -N0-1 mod W. Hagen Ploog, Dirk Timmermann |
| 2000 | On Solving Stack-Based Incremental Satisfiability Problems. Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah |
| 2000 | On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | On the Road to a Mobile Information Society. Dirk Friebel |
| 2000 | OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha P. Chandrakasan |
| 2000 | Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh |
| 2000 | Output Prediction Logic: A High-Performance CMOS Design Technique. Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen |
| 2000 | PEAS-III: An ASIP Design Environment. Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi |
| 2000 | Power-Sensitive Multithreaded Architecture. John S. Seng, Dean M. Tullsen, George Z. N. Cai |
| 2000 | Predictive Strategies for Low-Power RTOS Scheduling. Pavan Kumar, Mani B. Srivastava |
| 2000 | Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000 |
| 2000 | Processors for Mobile Applications. Farinaz Koushanfar, Miodrag Potkonjak, Vandana Prabhu, Jan M. Rabaey |
| 2000 | Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds. Dimitrios Kagaris, Spyros Tragoudas |
| 2000 | Rectilinear Block Placement Using B*-Trees. Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang |
| 2000 | Reducing Cost and Tolerating Defects in Page-based Intelligent Memory. Mark Oskin, Diana Keen, Justin Hensley, Lucian Vlad Lita, Frederic T. Chong |
| 2000 | Representing and Scheduling Looping Behavior Symbolically. Steve Haynal, Forrest Brewer |
| 2000 | Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows. Wander O. Cesário, Ahmed Amine Jerraya, Zoltan Sugar, Imed Moussa |
| 2000 | SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku |
| 2000 | Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson |
| 2000 | Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar |
| 2000 | Sleipnir - An Instruction-Level Simulator Generator. Tor E. Jeremiassen |
| 2000 | Source-Level Transformations for Improved Formal Verification. Brian D. Winters, Alan J. Hu |
| 2000 | Static Timing Analysis with False Paths. Haizhou Chen, Bing Lu, Ding-Zhu Du |
| 2000 | Symbolic Binding for Clustered VLIW ASIPs. Satish Pillai, Margarida F. Jacome |
| 2000 | Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies. Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung |
| 2000 | The Birth of the Baby. Hilary J. Kahn, R. B. E. Napper |
| 2000 | The Future of Populist Parallelism. Gregory F. Pfister |
| 2000 | The M·CORE Afzal Malik, Bill Moyer, Dan Cermak |
| 2000 | Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation. Qiang Cao, Josep Torrellas, H. V. Jagadish |
| 2000 | Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. Tong Xiao, Malgorzata Marek-Sadowska |
| 2000 | Xtensa with User Defined DSP Coprocessor Microarchitectures. Gülbin Ezer |