| 1999 | 32-Bit Architectures for Embedded Systems. Ronald Stence |
| 1999 | A Compiler-Assisted Data Prefetch Controller. Steven P. Vanderwiel, David J. Lilja |
| 1999 | A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211. Tor E. Jeremiassen |
| 1999 | A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G. |
| 1999 | A Fast Median Filter Using AltiVec. Priyadarshan Kolte, Roger Smith, Su Wen |
| 1999 | A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping. Kang Yi, Seong Yong Ohm |
| 1999 | A High-Performance Hardware-Efficient Memory Allocation Technique and Design. Hasan Cam, Mostafa I. H. Abd-El-Barr, Sadiq M. Sait |
| 1999 | A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications. Mauro Olivieri, Alessandro Trifiletti, Alessandro De Gloria |
| 1999 | A Methodology for Rapid Prototyping of Analog Systems. Sree Ganesan, Ranga Vemuri |
| 1999 | A New Development Tool with the IEEE-ISTO. Ronald Stence |
| 1999 | A New Weight Set Generation Algorithm for Weighted Random Pattern Generation. Hangkyu Lee, Sungho Kang |
| 1999 | A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. Bong-Il Park, In-Cheol Park, Chong-Min Kyung |
| 1999 | A Robust Solution to the Timing Convergence Problem in High-Performance Design. Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking |
| 1999 | A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing. Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada |
| 1999 | A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations. William L. Freking, Keshab K. Parhi |
| 1999 | ActiveOS: Virtualizing Intelligent Memory. Mark Oskin, Frederic T. Chong, Timothy Sherwood |
| 1999 | An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages. Chunhong Chen, Majid Sarrafzadeh |
| 1999 | An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou |
| 1999 | An Efficient Functional Coverage Test for HDL Descriptions at RTL. Chien-Nan Jimmy Liu, Jing-Yang Jou |
| 1999 | An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment. HyunJin Kim, Jongchul Shin, Sungho Kang |
| 1999 | An Environment for Exploring Low Power Memory Configurations in System Level Design. Sari L. Coumeri, Donald E. Thomas |
| 1999 | An Even Wiring Approach to the Ball Grid Array Package Routing. Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai |
| 1999 | An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. K. K. Lee, D. F. Wong |
| 1999 | An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. Qi Wang, Sarma B. K. Vrudhula |
| 1999 | Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning Trees. Guo-Hui Lin, Guoliang Xue, Defang Zhou |
| 1999 | Architectural Synthesis of Timed Asynchronous Systems. Brandon M. Bachman, Hao Zheng, Chris J. Myers |
| 1999 | Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. Lucian Codrescu, D. Scott Wills |
| 1999 | Area, Performance, and Yield Implications of Redundancy in On-Chip Caches. Tom Thomas, Brian Anthony |
| 1999 | Automatic Error Correction of Tri-State Circuits. Dirk W. Hoffmann, Thomas Kropf |
| 1999 | Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. Avinash K. Gautam, V. Visvanathan, S. K. Nandy |
| 1999 | BDD Decomposition for Efficient Logic Synthesis. Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal |
| 1999 | Benchmarking, Selection and Debugging of Microcontrollers. Alan Weiss |
| 1999 | CAD Techniques for Embedded Systems-on-Silicon. Wayne H. Wolf |
| 1999 | Cache Optimization for Memory-Resident Decision Support Commercial Workloads. Pedro Trancoso, Josep Torrellas |
| 1999 | CalmRISC Kyoung-Mook Lim, Seh-Woong Jeong, Yong-Chun Kim, Seung-Jae Jeong, Hong-Kyu Kim, Yang-Ho Kim, Bong-Young Chung, Hyung-Lae Roh, H. S. Yang |
| 1999 | Characterization of Java Applications at Bytecode and Ultra-SPARC Machine Code Levels. Ramesh Radhakrishnan, Juan Rubio, Lizy Kurian John |
| 1999 | Compositional Software Synthesis of Communicating Processes. Xiaohan Zhu, Bill Lin |
| 1999 | Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD. Hen-Ming Lin, Jing-Yang Jou |
| 1999 | Conceptual Modeling and Simulation. Walling R. Cyre |
| 1999 | Customization of a CISC Processor Core for Low-Power Applications. You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung |
| 1999 | DSP for the Third Generation Wireless Communications. Uming Ko, Mike McMahan, Edgar Auslander |
| 1999 | Decomposition of Finite State Machines for Area, Delay Minimization. Rupesh S. Shelar, Madhav P. Desai, H. Narayanan |
| 1999 | Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions. Maitham Shams, Mohamed I. Elmasry |
| 1999 | Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. Sumio Morioka, Yasunao Katayama |
| 1999 | Design and Evaluation of a Selective Compressed Memory System. Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim |
| 1999 | Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. Paul Chang, Brion L. Keller, Sarala Paliwal |
| 1999 | Design and Synthesis of Monotonic Circuits. Tyler Thorp, Gin Yee, Carl Sechen |
| 1999 | Design for Testability to Combat Delay Faults. Jacob Savir |
| 1999 | Designing the M·CORE Jeff Scott, Lea Hwang Lee, Ann Chin, John Arends, Bill Moyer |
| 1999 | Detailed Characterization of a Quad Pentium Pro Server Running TPC-D. Qiang Cao, Josep Torrellas, Pedro Trancoso, Josep Lluís Larriba-Pey, Bob Knighten, Youjip Won |
| 1999 | Dynamic Branch Decoupled Architecture. Akhilesh Tyagi, Hon-Chi Ng, Prasant Mohapatra |
| 1999 | Efficient Crosstalk Estimation. Martin Kuhlmann, Sachin S. Sapatnekar, Keshab K. Parhi |
| 1999 | Efficient Fixpoint Computation for Invariant Checking. Kavita Ravi, Fabio Somenzi |
| 1999 | Energy and Performance Improvements in Microprocessor Design Using a Loop Cache. Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George D. Stamoulis |
| 1999 | Evaluation of Computing in Memory Architectures for Digital Image Processing Applications. David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor |
| 1999 | Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | FlexRAM: Toward an Advanced Intelligent Memory System. Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik |
| 1999 | Formal Verification of Synthesized Analog Designs. Abhijit Ghosh, Ranga Vemuri |
| 1999 | Forty Five Years of Computer Architecture-All That's Old is New Again. Harvey G. Cragon |
| 1999 | Generic Universal Switch Blocks. Michael Shyu, Yu-Dong Chang, Guang-Ming Wu, Yao-Wen Chang |
| 1999 | Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory. Romain Kamdem, Alain Fonkoua, Andre Zenatti |
| 1999 | High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. Jae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr. |
| 1999 | Implicit Verification of Structurally Dissimilar Arithmetic Circuits. Ted Stanion |
| 1999 | Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter. Rolf Hakenes, Yiannos Manoli |
| 1999 | Improving Witness Search Using Orders on States. Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham |
| 1999 | Load-Balancing Branch Target Cache and Prefetch Buffer. Chi-Hung Chi, Jun-Li Yuan |
| 1999 | Low-Power Radix-4 Combined Division and Square Root. Alberto Nannarelli, Tomás Lang |
| 1999 | Multi-Level Logic Minimization through Fault Dictionary Analysis. Ronald W. Mehler, M. Ray Mercer |
| 1999 | Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. Tomás Lang, Javier D. Bruguera |
| 1999 | Multiple Paths Sensitization of Digital Oscillation Built-In Self Test. Christian Dufaza |
| 1999 | Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis. Ashok Kumar, Magdy A. Bayoumi |
| 1999 | On Detecting Bridges Causing Timing Failures. Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu |
| 1999 | On State Assignment of Finite State Machines Using Hypercube Embedding Approach. Imtiaz Ahmad, Raza Ul-Mustafa |
| 1999 | On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors. Srivatsan Srinivasan, Lizy Kurian John |
| 1999 | On-Line BIST for Testing Analog Circuits. Jaime Velasco-Medina, Iyad Rayane, Michael Nicolaidis |
| 1999 | Performance Driven Optimization of Network Length in Physical Placement. Wilm E. Donath, Prabhakar Kudva, Lakshmi N. Reddy |
| 1999 | Performance Evaluation of Configurable Hardware Features on the AMD-K5. Mike Clark, Lizy Kurian John |
| 1999 | Performance and Reliability Verification of C6201/C6701 Digital Signal Processors. Nagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor |
| 1999 | Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study. William Fornaciari, Donatella Sciuto, Cristina Silvano |
| 1999 | Preference-Driven Hierarchical Hardware/Software Partitioning. Gang Quan, Xiaobo Hu, Garrison W. Greenwood |
| 1999 | Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999 |
| 1999 | Pursuing the Performance Potential of Dynamic Cache Line Sizes. Peter van Vleet, Eric J. Anderson, Lindsay Brown, Jean-Loup Baer, Anna R. Karlin |
| 1999 | SOI Implementation of a 64-Bit Adder. J. V. Tran, Farnaz Mounes-Toussi, S. N. Storino, D. L. Stasiak |
| 1999 | Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor. Nathan Kalyanasundharam, Nital Patwa |
| 1999 | Software Synthesis for Complex Reactive Embedded Systems. Felice Balarin, Massimiliano Chiodo |
| 1999 | Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy |
| 1999 | Synthesis of Arrays and Records. Pradip K. Jha, Steven Barnfield, John B. Weaver, Rudra Mukherjee, Reinaldo A. Bergamaschi |
| 1999 | Synthesis of Pseudo Kronecker Lattice Diagrams. Per Lindgren, Rolf Drechsler, Bernd Becker |
| 1999 | System Design: Traditional Concepts and New Paradigms. Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli |
| 1999 | System-on-a-Chip Bus Architecture for Embedded Applications. Peter James Aldworth |
| 1999 | The MARCO/DARPA Gigascale Silicon Research Center. Kurt Keutzer, A. Richard Newton |
| 1999 | The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. Brian R. Fisk, R. Iris Bahar |
| 1999 | The Specialization of General Purpose Processor Architecture Elements for Programmable Digital Signal Processors. Donald Steiss |
| 1999 | Transmission Line Clock Driver. Matthew E. Becker, Thomas F. Knight Jr. |
| 1999 | TriMedia CPU64 Application Development Environment. Evert-Jan D. Pol, Bas Aarts, Jos T. J. van Eijndhoven, P. Struik, Pieter van der Wolf, Frans Sijstermans, M. J. A. Tromp, Jan-Willem van de Waerdt |
| 1999 | TriMedia CPU64 Application Domain and Benchmark Suite. A. K. Riemens, Kees A. Vissers, R. J. Schutten, Gerben J. Hekstra, G. D. La Hei, Frans Sijstermans |
| 1999 | TriMedia CPU64 Architecture. Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel |
| 1999 | TriMedia CPU64 Design Space Exploration. Gerben J. Hekstra, G. D. La Hei, Peter Bingley, Frans Sijstermans |
| 1999 | Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. Abhijit Jas, Nur A. Touba |
| 1999 | Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. Eduard Cerny, Fen Jin |
| 1999 | Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya |
| 1999 | Yield Optimization by Design Centering and Worst-Case Distance Analysis. G. S. Samudra, H. M. Chen, D. S. H. Chan, Yaacob Ibrahim |