ICCD C

114 papers

YearTitle / Authors
1993A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology.
Debabrata Ghosh, S. K. Nandy
1993A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture.
Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara
1993A C-Testable Carry-Free Divider.
Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi
1993A Comparative Evaluation of Adders Based on Performance and Testability.
Rathish Jayabharathi, Thomas Thomas, Earl E. Swartzlander Jr.
1993A Comparison of Synchronous and Asynchronous FSMD Designs.
Richard Auletta, Robert B. Reese, Cherrice Traver
1993A Field Programmable Accelerator for Compiled-Code Applications.
David M. Lewis, Marcus van Ierssel, Daniel H. Wong
1993A Framework for Specifying and Designing Pipelines.
Mark D. Aagaard, Miriam Leeser
1993A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits.
Hungse Cha, Janak H. Patel
1993A Memory Controller with an Integrated Graphics Processor.
John Watkins, Raymond Roth, Michael Hsieh, William Radke, Donald Hejna, Byung Kim, Richard Tom
1993A New High Performance Field Programmable Gate Array Family.
Telle Whitney, Jeff Schlageter
1993A New Modulo 2
Artur Wrzyszcz, David Milford
1993A Note About the Correction Cycle of High Radix Booth's Multiplication.
Gong Guo, Mohammad Ashtijou
1993A Novel Clock Distribution System for CMOS VLSI.
Kenichi Ishibashi, Takehisa Hayashi, Toshio Doi, Noboru Masuda, Akira Yamagiwa, Toshihiro Okabe
1993A Partial Scan Cost Estimation Method at the System Level.
Scott Chiu, Christos A. Papachristou
1993A Path Sensitization Approach to Area Reduction.
Hsi-Chuan Chen, Siu-Wing Cheng, Yaun-Chung Hsu, David Hung-Chang Du
1993A Reconfiguration-Based Yield Enhancement System.
Jagannathan Narasimhan, Kazuo Nakajima
1993A Recursive Technique for Computing Lower-Bound Performance of Schedules.
Michel Langevin, Eduard Cerny
1993A Split Data Cache for Superscalar Processors.
Rodney Boleyn, James Debardelaben, Vivek Tiwari, Andrew Wolfe
1993A Systolic Architecture for High Speed Pipelined Memories.
Alex G. Dickinson, Chris J. Nicol
1993A Systolic Array for Approximate String Matching.
Raghu Sastry, N. Ranganathan
1993A Three-Dimensional Mesh Multiprocessor System Using Board-to-Board Free-Space Optical Interconnects: COSINE-III.
Toshikazu Sakano, Takao Matsumoto, Kazuhiro Noguchi
1993A Vector Memory System Based on Wafer-Scale Integrated Memory Arrays.
Tzi-cker Chiueh
1993ACES: A Transient Simulation Strategy for Integrated Circuits.
Anirudh Devgan, Ronald A. Rohrer
1993AMBIANT: Automatic Generation of Behavioral Modifications for Testability.
Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir
1993ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits.
Chin-Long Wey, Ming-Der Shieh, P. David Fisher
1993About Set and Skewed Associativity on Second-Level Caches.
André Seznec
1993An Adaptive Technique for Dynamic Rollback in Concurrent Event-Driven Fault Simulation.
Laura Farinetti, Pier Luca Montessoro
1993An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems.
Tod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello
1993An Analysis of Path Sensitization Criteria.
João P. Marques Silva, Karem A. Sakallah
1993An Efficient Symbolic Design Verification System.
Jaehong Park, M. Ray Mercer
1993An Efficient Unique State Coding Algorithm for Signal Transition Graphs.
Enric Pastor, Jordi Cortadella
1993An Exact Rectilinear Steiner Tree Algorithm.
Jeffrey S. Salowe, David M. Warme
1993An Integrated Environment for Concurrent Development of a Pixel Processor ASIC and Application Software.
Raymond Roth, John Watkins, Michael Hsieh, William Radke, Donald Hejna, Richard Tom, Byung Kim
1993An Intelligent I-Cache Prefetch Mechanism.
Honesty C. Young, Eugene J. Shekita
1993Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment.
Ravindranath Naiknaware
1993Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage Sources.
Perng-Shyong Lin, Charles A. Zukowski
1993Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000.
Trung A. Diep, Mikko H. Lipasti, John Paul Shen
1993Area and Performance Comparison of Pipelined RISC Processors Implementing Different Precise Interrupt Methods.
Chia-Jiu Wang, Frank Emnett
1993Beyond Superscalar Using FPGAs.
Christian Iseli, Eduardo Sanchez
1993Bit-Splitting for Testability Enhancement in Scan-Based Design.
Xiaodong Xie, Alexander Albicki
1993Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs.
Kaushik Roy, Sudip Nag, Santanu Dutta
1993Cluster-Oriented Scheduling in Pipelined Data Path Syntesis.
Ching-Tang Chang, Kenneth Rose, Robert A. Walker
1993Complex Gate Performance Improvement by Jog Insertion into Transistor Gates.
Ronald D. Hindmarsh
1993Computer-Aided Redesign of VLSI Circuits for Hot-Carrier Reliability.
Ping-Chung Li, Ibrahim N. Hajj
1993Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters.
Abhijit Chatterjee, Rabindra K. Roy
1993Derivation of a DRAM Memory Interface by Sequential Decomposition.
Kamlesh Rath, Bhaskar Bose, Steven D. Johnson
1993Desgin for Testability of Asynchronous Sequential Circuits.
Jayashree Saxena, Dhiraj K. Pradhan
1993Design Guidelines and Testability Assessment.
Brian R. Wilkins, C. Shi
1993Design Methodology for GMICRO
Susumu Narita, Fumio Arakawa, Kunio Uchiyama, Ikuya Kawasaki
1993Design for Testability: Today and in the Future.
Thomas W. Williams
1993Design of the Intel Pentium
Avtar Saini
1993Determining Cost-Effective Multiple Issue Processor Designs.
Thomas M. Conte, William H. Mangione-Smith
1993Economics in Design and Test.
Chryssa Dislis, Anthony P. Ambler, I. D. Dear, J. H. Dick
1993Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems.
Santhanam Srinivasan, Niraj K. Jha
1993Efficient Symbolic Support Manipulation.
Bill Lin
1993Efficient Verification of Symmetric Concurrent Systems.
C. Norris Ip, David L. Dill
1993Evaluation of an Object-Caching Coprocessor Design for Object-Oriented Systems.
J. Morris Chang, Edward F. Gehringer
1993Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition Relation.
Gianpiero Cabodi, Paolo Camurati
1993Fast CRC Calculation.
René J. Glaise, X. Jacquart
1993Fast Timing Analysis for Hardware-Software Co-Synthesis.
Wei Ye, Rolf Ernst, Thomas Benner, Jörg Henkel
1993Fault-Tolerant Content Addressable Memory.
Jien-Chung Lo
1993Fidelity and Near-Optimality of Elmore-Based Routing Constructions.
Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins
1993Formal Semantics of VHDL for Verification of Circuit Designs.
Xin Hua, Hantao Zhang
1993Functional Fault Models and Gate Level Coverage for Sequential Architectures.
Giacomo Buonanno, Franco Fummi, Donatella Sciuto
1993Global Mobility Based Scheduling.
Usha Prabhu, Barry M. Pangrle
1993Hardware Self-Tuning and Circuit Performance Monitoring.
Ted Kehl
1993Hardware Verification Using Symbolic State Transition Graphs.
Pinhong Chen, Jyuo-Min Shyu, Liang-Gee Chen
1993Heuristic Minimization of Synchronous Relations.
Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton
1993Hierarchical Constraint Solving in the Parametric Form with Applications to Efficient Symbolic Simulation Based Verification.
Prabhat Jain, Ganesh Gopalakrishnan
1993High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques.
Miodrag Potkonjak, Sujit Dey, Zia Iqbal, Alice C. Parker
1993Hybrid Number Representations with Bounded Carry Propagation Chains.
Dhananjay S. Phatak, Israel Koren, Hoon Choi
1993Influence of Error Correlations on the Signature Analysis Aliasing.
Régis Leveugle, X. Delord, Gabriele Saucier
1993Library-Adaptively Integrated Data Path Synthesis for DSP Systems.
Jer-Min Jou, Shiann-Rong Kuang
1993Logic Optimization with Multi-Output Gates.
Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton
1993Low-Power Driven Technology Mapping under Timing Constraints.
Bill Lin, Hugo De Man
1993Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow Graphs.
Yuan Hu, Ahmed Ghouse, Bradley S. Carlson
1993MIXER: Mixed-Signal Fault Simulator.
Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
1993Multiple-Page Translation for TLB.
Lishing Liu
1993Neighbour State Transition Method for VLSI Optimization Problems.
Dian Zhou, F. Tsui
1993Newton: Performance Improvement Through Comparative Analysis.
Lyle D. Kipp, David J. Kuck
1993Optimal Scheduling of Finite-State Machines.
Ti-Yen Yen, Wayne H. Wolf
1993Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project.
Klaus ten Hagen, Heinrich Meyr
1993Phi-Test: Perfect Hashed Index Test for Test Response Validation.
Rajiv Gupta
1993Physically Realizable Gate Models.
Paul R. Stephan, Robert K. Brayton
1993Pica: An Ultra-Light Processor for High-Througput Applications.
D. Scott Wills, W. Stephen Lacy, Huy Cat, Michael A. Hopper, Ashutosh Razdan, Sek M. Chai
1993Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph.
Shang-E Tai, Debashis Bhattacharya
1993Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '93, Cambridge, MA, USA, October 3-6, 1993
1993Pseudoexhaustive BIST for Sequential Circuits.
Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
1993Quiescent Current Monitoring to Improve the Reliability of Electronic Systems in Space Radiation Environments.
F. L. Vargas, Michael Nicolaidis, Bernard Courtois
1993Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation.
Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown
1993Reducing the Cost of Test Pattern Generation by Information Reusing.
Weidong Li, Carl McCrosky, Mostafa I. H. Abd-El-Barr
1993SMAC: A Scene Matching Chip.
N. Ranganathan, Raghu Sastry, Raguveer Venkatesan, Joseph W. Yoder, David C. Keezer
1993Some Results on the Complexity of Boolean Functions for Table Look Up Architectures.
Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993Specification and Synthesis of Mixed-Mode Systems: Experiments in a VHDL Environment.
P. A. Subrahmanyam, Josep M. Espinalt, Meng-Lin Yu
1993Speculative Computation for Coprocessor Synthesis.
Ulrich Holtmann, Rolf Ernst
1993Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine.
Hideki Ando, Chikako Nakanishi, Hirohisa Machida, Tetsuya Hara, Satoru Kishida, Masao Nakaya
1993Statistical Timing Optimization of Combinatorial Logic Circuits.
Horng-Fei Jyu, Sharad Malik
1993String Matching on IDP: A String Matching Algorithm for Vector Processors and Its Implementation.
Yusuke Mishina, Keiji Kojima
1993Strongly NP-Hard Discrete Gate Sizing Problems.
Wing Ning Li
1993Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip.
Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Peeters
1993Symbolic Analysis Methods for Masks, Circuits, and Systems.
Randal E. Bryant
1993Synthesis of Controllers from Interval Temporal Logic Specification.
Masahiro Fujita, Shinji Kono
1993Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan.
Sandeep Bhatia, Niraj K. Jha
1993System Factorization in Codesign: A Case Study of the Use of Formal Techniques to Achieve Hardware-Software Decomposition.
Bhaskar Bose, M. Esen Tuna, Steven D. Johnson
1993System-Level Specification of Instruction Sets.
Todd A. Cook, Paul D. Franzon, Edwin A. Harcourt, Thomas K. Miller III
1993Test Path Generation and Test Scheduling for Self-Testable Designs.
Alex Orailoglu, Ian G. Harris
1993The PowerPC 601 Design Methodology.
Timothy B. Brodnax, Mike Schiffli, Floyd Watson
1993The Splash 2 Processor and Applications.
Jeffrey M. Arnold, Duncan A. Buell, Dzung T. Hoang, Daniel V. Pryor, Nabeel Shirazi, Mark R. Thistle
1993The Spring Scheduling Co-Processor: A Scheduling Accelerator.
Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems
1993The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem.
Samit Chaudhuri, Robert A. Walker, John Mitchell
1993Towards a Methodology for the Formal Hierarchical Verification.
Sofiène Tahar, Ramayya Kumar
1993Trail: A Track-Based Logging Disk Architecture for Zero-Overhead Writes.
Tzi-cker Chiueh
1993VLSI Design of On-Line Add/Multiply Algorithms.
Ali Skaf, Alain Guyot
1993Wearable Computers: Merging Information Space with the Workspace.
Daniel P. Siewiorek