| 1990 | 2.5 Gbits/sec telecommunications gate array. N. Hendrickson, R. Langer, T. Coe, M. Vana, I. Deyhimy |
| 1990 | 68040 integer module. Kirk Holden, Renny Eisele, Mike Kobe, James Raleigh, Thomas Spohrer |
| 1990 | 68040 memory modules and bus controller. Brad Martin, Steve McMahan, Lal Sood |
| 1990 | A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations. Akira Katsuno, Hiromasa Takahashi, Hajime Kubosawa, Tomio Sato, Atsuhiro Suga, Gensuke Goto |
| 1990 | A 75 MHz CMOS digital convolver. P. J. Rose, B. G. Koether |
| 1990 | A class of close-to-optimum adder trees allowing regular and compact layout. Zhi-Jian Mou, Francis Jutand |
| 1990 | A design environment for high performance VLSI signal processing. Sailesh K. Rao, Mehdi Hatamian, Bryan D. Ackland |
| 1990 | A file-based adaptive prefetch caching design. F. Warren Shih, Tze Chiang Lee, Shauchi Ong |
| 1990 | A floating point unit for the 68040. Shawn McCloud, Donnie Anderson, Chris DeWitt, Chris Hinds, Ying-Wai Ho, Danny Marquette, Eric Quintana |
| 1990 | A functional diagnostics methodology. Ramachandra P. Kunda, Bharat Deep Rathi |
| 1990 | A global feedback detection algorithm for VLSI circuits. H.-C. Shih, Predrag G. Kovijanic, Rahul Razdan |
| 1990 | A hierarchical floorplanning approach. Massoud Pedram, Bryan Preas |
| 1990 | A linear time algorithm for optimal CMOS functional cell layouts. Po-Yang F. Lin, Kazuo Nakajima |
| 1990 | A parallel algorithm for constructing binary decision diagrams. Shinji Kimura, Edmund M. Clarke |
| 1990 | A parameter adjustment method for analog circuits based on convex fuzzy decision using constraints of satisfactory level. Masaki Hashizume, Takeomi Tamesada, Koji Nii |
| 1990 | A pipelined microprocessor for logic programming languages. Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Hideki Andou, Kiyohiro Furutani |
| 1990 | A reduced area scheme for carry-select adders. Akhilesh Tyagi |
| 1990 | A strategy for avoiding pipeline interlock delays in a microprocessor. Toyohiko Yoshida, Masahito Matsuo, Tatsuya Ueda, Yuichi Saito |
| 1990 | A trace-driven analysis of the 'wrap-around' network. Caroline Benveniste, Yarsun Hsu |
| 1990 | ASIC design using the high-level synthesis system CALLAS: a case study. Michael Koster, Martin Geiger, Peter Duzy |
| 1990 | Accurate interconnect modeling for high frequency LSI/VLSI circuits and systems. C. G. Lin-Hendel |
| 1990 | An analog parallel distributed solution to the shortest path problem. Scott E. Ritter, K. Soumyanath |
| 1990 | An approach to 150 K gate low power ECL cell based integrated circuits. G. Taylor, G. Sanguinetti, R. Lane |
| 1990 | An area estimation technique for module generation. Arun Rajanala, Akhilesh Tyagi |
| 1990 | An area-efficient reconfigurable binary tree architecture. Chung-Han Chen, Nian-Feng Tzeng |
| 1990 | An edge based netlist extractor for IC layouts. Sandeep Aranake, Anil Dikshit, A. Arun |
| 1990 | An efficient parallel algorithm for channel routing. Sridhar Krishnamurthy, Joseph F. JáJá |
| 1990 | An improved algorithm for the minimization of mixed polarity Reed-Muller representations. J. M. Saul |
| 1990 | Application specific microprocessor [NS3200/EP family]. Gideon D. Intrater, Dan Biran |
| 1990 | Approximate time-domain models of three-dimensional interconnects. Hansruedi Heeb, Albert E. Ruehli |
| 1990 | Architectures for pipelined Wallace tree multiplier-accumulators. King Fai Pang |
| 1990 | Associative and data processing Mbit-DRAM. Oskar Kowarik, Rainer Kraus, Kurt Hoffmann, Karl H. Horninger |
| 1990 | Automatic classification of node types in switch-level descriptions. David T. Blaauw, Prithviraj Banerjee, Jacob A. Abraham |
| 1990 | Automatic generation of control circuits in pipelined DSP architectures. Ching-Yi Wang, Keshab K. Parhi |
| 1990 | Automatic layout generation for mixed analog-digital VLSI neural chips. David J. Chen, Bing J. Sheu |
| 1990 | BiCMOS Futurebus transceiver. T. Fletcher, E. Hahn, J. West |
| 1990 | BiCMOS design overview and implementation methodology. Ramesh S. Iyer |
| 1990 | BiCMOS fault models: is stuck-at adequate? Marc E. Levitt, Kaushik Roy, Jacob A. Abraham |
| 1990 | Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams. Hitomi Sato, Norikazu Takahashi, Yusuke Matsunaga, Masahiro Fujita |
| 1990 | Built-in self-test with weighted random pattern hardware. Franc Brglez, Clay S. Gloster Jr., Gershon Kedem |
| 1990 | Cache design for high performance computers with BiCMOS VLSIs. M. Morioka, K. Kurita, H. Kobayashi, H. Sawamoto |
| 1990 | Combined hardware selection and pipelining in high performance data-path design. Stefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man |
| 1990 | Compacting randomly generated test sets. James H. Aylor, James P. Cohoon, E. L. Feldhousen, Barry W. Johnson |
| 1990 | Complexity issues in RAM-DFE design for magnetic disk drives. Philip S. Bednarz, William L. Abbott, Kevin D. Fisher, John M. Cioffi |
| 1990 | Computer systems employing reconfigurable board-to-board free-space optical interconnections: COSINE-1 and -2. Takao Matsumoto, Toshikazu Sakano, Kazuhiro Noguchi, Tomoko Sawabe |
| 1990 | Concurrent testing of VLSI circuits using conservative logic. Gnanasekaran Swaminathan, James H. Aylor, Barry W. Johnson |
| 1990 | DEBBIE: a configurable user interface for CAD frameworks. Marcus S. Yoo, Arding Hsu |
| 1990 | Derivation of signal flow direction in MOS VLSI: an alternative. W. De Rammelaere, Ivo Bolsens, Luc J. M. Claesen, Hugo De Man |
| 1990 | Design aids and test results for laser-programmable logic arrays. David L. Allen, Richard Goldenberg |
| 1990 | Design and application trade-offs between high-density and high-speed ASICs. Patrick Lampin, J. C. Le Garrec, C. Marion, J. P. Mifsud, T. Mille, S. Nicot, B. Rousseau, R. Saura, T. Tatry, C. John Glossner, R. D. Kilmoyer |
| 1990 | Design for routability of a high-density gate array. Dick W. Harberts, Dré A. J. M. van den Elshout, Harry J. M. Veendrick |
| 1990 | Design issues of a rate 8/10 matched-spectral-null trellis code chip for partial response channels. C. Bernard Shung, Paul H. Siegel, Hemant K. Thapar, Razmik Karabed |
| 1990 | Design of a custom processing unit based on Intel i486 architectures and performances trade-offs. Jean-Luc Peter |
| 1990 | Design of repairable and fully testable folded PLAs. Chin-Long Wey, Jyhyeung Ding |
| 1990 | Design of robustly testable static CMOS parity trees derived from binary decision diagrams. Niraj K. Jha, Carol Q. Tong |
| 1990 | Digital magnetic recording systems. Jack Keil Wolf |
| 1990 | Early resolution of address translation in cache design. Kien A. Hua, A. Hunt, L. Liu, J.-K. Peir, D. Pruett, J. Temple |
| 1990 | Empirical evaluation of randomly-wire multistage networks. Tom Leighton, Derek Linsinski, Bruce M. Maggs |
| 1990 | Estimating aliasing in CA and LFSR based signature registers. D. Michael Miller, Shujian Zhang, Werner Pries, Robert D. McLeod |
| 1990 | Experiments with an efficient heuristic algorithm for local microcode generation. M. Mahmood, Farhad Mavaddat, M. I. Elmastry |
| 1990 | Exploitation of operation-level parallelism in a processor of the CRAY X-MP. Sriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu |
| 1990 | Fast parallel communication on mesh connected machines with low buffer requirements. Fillia Makedon, Adonios Simvonis |
| 1990 | Fault grading of large digital systems. Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham |
| 1990 | Fault tolerance in RNS: an efficient approach. Damu Radhakrishnan, Taejin Pyon |
| 1990 | Figures of merit for system path time estimation. C. George Hsi, Stuart G. Tucker |
| 1990 | Formal semantics of UDL/I and its applications to CAD/DA tools. Hiroto Yasuura, Nagisa Ishiura |
| 1990 | Formal verification of cache systems using refinement relations. Paul Loewenstein, David L. Dill |
| 1990 | HAL III: function level hardware logic simulation. Shigeru Takasaki, Nobuyoshi Nomizu, Yoshihiro Hirabayashi, Hiroshi Ishikura, Masahiro Kurashita, Nobuhiko Koike, Toshiyuki Nakata |
| 1990 | Heuristic minimization of Boolean relations using testing techniques. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
| 1990 | High speed VLSI logic simulation using bitwise operations and parallel processing. Young-Hyun Jun, Ibrahim N. Hajj, Sang-Heon Lee, Song-Bai Park |
| 1990 | Logic synthesis for programmable logic devices. TingTing Hwang, Robert Michael Owens, Mary Jane Irwin |
| 1990 | Minimization of multioutput TANT networks for unlimited fan-in network model. Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Tuhar Shah |
| 1990 | Modular BIST concept for microprocessors. Hartmut C. Ritter, Thomas M. Schwair |
| 1990 | Multiterminal-net routing by grid stretching. Teofilo F. Gonzalez, Si-Qing Zheng |
| 1990 | MxSICO: a silicon compiler for mixed analog digital circuits. Ertugrul Berkcan |
| 1990 | New ideas on symbolic manipulations of finite state machines. Christian Berthet, Olivier Coudert, Jean Christophe Madre |
| 1990 | On the estimation of logic complexity for design automation applications. Devadas Varma, Eliezer A. Trachtenberg |
| 1990 | On-the-fly circuit to measure the average working set size. Kwangkeun Yi, Luddy Harrison |
| 1990 | Optimized bit level architectures for IIR filtering. O. C. McNally, John V. McCanny, Roger F. Woods |
| 1990 | Parallel digital image restoration using adaptive VLSI neural chips. Ji-Chien Lee, Bing J. Sheu |
| 1990 | Pin assignment for improved performance in standard cell design. Malgorzata Marek-Sadowska, Shen P. Lin |
| 1990 | Placement algorithms for CMOS cell synthesis. Dwight D. Hill, Marw A. Aranha, Donald D. Shugard |
| 1990 | Practical design assistance at register transfer level using a data path verifier. Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka |
| 1990 | Preliminary description of Tabula Rasa, an electrically reconfigurable hardware engine. Dwight D. Hill, Daniel R. Cassiday |
| 1990 | Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1990, Cambridge, MA, USA, 17-19 September, 1990 |
| 1990 | Pseudo pin assignment for single-layer over-the-cell routing. Howard H. Chen |
| 1990 | QRAM-Quick access memory system. Hideto Niijima, Nobuyuki Oba |
| 1990 | Real-time computing of optical flow using adaptive VLSI neuroprocessors. Wai-Chi Fang, Bing J. Sheu, Ji-Chien Lee |
| 1990 | Reliability analysis of a computer system for a data collection application. Andrew L. Reibman |
| 1990 | Reliable design of multichip nonblocking crossbars. Joydeep Ghosh, Anujan Varma |
| 1990 | Rule-based testability rule check program. Yasushi Koseko, C. Hiramine, Takuji Ogihara, Shinichi Murai |
| 1990 | SAP: design of a systolic array processor for computation in vision. Sanjay Nichani, N. Ranganathan |
| 1990 | SYLON-REDUCE: an MOS network optimization algorithms using permissible functions. Johnson Chan Limqueco, Saburo Muroga |
| 1990 | Simultaneous bidirectional signalling for IC systems. Kevin Lam, Larry R. Dennison, William J. Dally |
| 1990 | Submicron BiCMOS technologies for supercomputer and high speed system implementation. Bami Bastani, Madan Biswal, Ali A. Iranmanesh, C. Lage, L. Bouknight, Vida Ilderem, A. Solheim, W. Burger, Rajeeva Lahri, J. Small |
| 1990 | Synthesis of testable PLAs using adaptive heuristics for efficiency. Pradip Bose, Subir Bandyopadhyay, D. Dutta Majumder |
| 1990 | Task assignment by parallel simulated annealing. Ellen E. Witte, Roger D. Chamberlain, Mark A. Franklin |
| 1990 | Test architecture of the Motorola 68040. Thomas Spohrer, Danny Marquette, Michael Gallup |
| 1990 | Test generation in circuits constructed by input decomposition. Gueesang Lee, Mary Jane Irwin, Robert Michael Owens |
| 1990 | Testability driven synthesis of interacting finite state machines. Pranav Ashar, Srinivas Devadas, A. Richard Newton |
| 1990 | The complexity of adaptive annealing. Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken |
| 1990 | The fault dropping problem in concurrent event driven simulation. Silvano Gai, Pier Luca Montessoro |
| 1990 | The observability don't-care set and its approximations. Patrick C. McGeer, Robert K. Brayton |
| 1990 | Towards a VLSI packaging design support environment (PDSE); concepts and implementation. Jerzy W. Rozenblit, John L. Prince, Olgierd A. Palusinski |
| 1990 | VLSI asynchronous sequential circuit design. Suresh K. Gopalakrishnan, Gary K. Maki |
| 1990 | Vector processor design for parallel DSP systems using hierarchical behavioral description based synthesizer. Hiroshi Nakada, Naoya Sakurai, Yukiharu Kanayama, Naohisa Ohta, Kiyoshi Oguri |
| 1990 | Wavefront array processor for video applications. Ulrich Schmidt, Sönke Mehrgardt |