| 1989 | A 32-bit microprocessor with high performance bit-map manipulation instructions. Toru Shimizu, Shunichi Iwata, Yuichi Saito, Toyohiko Yoshida, Masahito Matsuo, Junichi Hinata, Kazunori Saito |
| 1989 | A VLSI module for IEEE floating-point multiplication/division/square root. Paul Y. Lu, Kevin Dawallu |
| 1989 | A VLSI residue arithmetic multiplier with fault detection capability. V. Bobin, D. Radhakrishnan |
| 1989 | A cached system architecture dedicated for the system IO activity on a CPU board. Michael M. Hsieh, Tek C. Wei, William Van Loo |
| 1989 | A channelless layout for multilevel synthesis with compiled cells. Gabriele Saucier, Régis Leveugle, Pierre Abouzeid |
| 1989 | A cost function based optimization technique for scheduling in data path synthesis. Hyunchul Shin, Nam Sung Woo |
| 1989 | A design of a memory management unit for object-based systems. Umakishore Ramachandran, M. Yousef Amin Khalidi |
| 1989 | A fast algorithm for mixed-radix conversion in residue arithmetic. Çetin Kaya Koç |
| 1989 | A fast floor planning algorithm for architectural evaluation. Michael C. McFarland |
| 1989 | A flexible architecture for neural networks. J. Ouali, Gabriele Saucier |
| 1989 | A framework for evaluating test pattern generation strategies. Tracy Larrabee |
| 1989 | A fuzzy logic controller with reconfigurable, cascadable architecture. Wayne D. Dettloff, Kathy E. Yount, Hiroyuki Watanabe |
| 1989 | A general-purpose video signal processor: architecture and programming. H. Dijkstra, Gerben Essink, A. J. M. Hafkamp, H. den Hengst, C. M. Huizer, Arthur H. M. van Roermund, Robert J. Sluyter, P. J. Snijder |
| 1989 | A generalized approach to the constrained cubical embedding problem. Bill Lin, A. Richard Newton |
| 1989 | A global floorplanning technique for VLSI layout. Alexander Herrigel, M. Glaser, Wolfgang Fichtner |
| 1989 | A hierarchical constraint graph generation and compaction system for symbolic layout. A. A. J. de Lange, J. S. J. de Lange, J. F. Vink |
| 1989 | A high performance BiCMOS 32-bit microprocessor. Yasuhiro Nakatsuka, Takashi Hotta, Shigeya Tanaka, Tadaaki Bandoh, Ryuichi Satomura, Syuichi Nakagami, Tetsuo Nakano, Atsuo Hotta, Takashi Moriyama, Shigemi Adachi, Shoji Iwamoto |
| 1989 | A logic network synthesis system, SYLON. S. Muroga, X. Q. Xiang, J. Limqueco, L. P. Lin, K. C. Chen |
| 1989 | A low-impedance load detector circuit for optical interconnects. Yang-Tung Huang, Raymond K. Kostuk |
| 1989 | A microprogrammable VLSI routing controller for HARTS. James W. Dolter, Parmesh Ramanathan, Kang G. Shin |
| 1989 | A module-sliced approach for high yield VLSI/WSI processors. Yi-Chieh Chang, Kang G. Shin |
| 1989 | A novel message switch for highly parallel systems. Shiwei Wang, Yarsun Hsu, C. J. Tan |
| 1989 | A system simulation environment within Digital. Quinn Canfield, Paul Barford, Paul Kinzelman, Cary Trlica |
| 1989 | A systolic approach to multistage interconnection network design. Chung-Han Chen, Laxmi N. Bhuyan |
| 1989 | A test generation system for path delay faults. Srinivas Patil, Sudhakar M. Reddy |
| 1989 | A yield model for the evaluation of topologically constrained chip architectures. Bruno Ciciani, Giuseppe Iazeolla |
| 1989 | Accurate prediction of physical design characteristics for random logic. Massoud Pedram, Bryan Preas |
| 1989 | Adaptive and pipelined VLSI designs for tree-based codes. Amar Mukherjee, N. Ranganathan, Mostafa A. Bassiouni |
| 1989 | An 80 MFLOPS floating-point engine in the Intel i860(TM) processor. Hon P. Sit, Monica Rosenrauch Nofal, Sunhyuk Kimn |
| 1989 | An IBM second generation RISC processor architecture. Randy D. Groves, Richard R. Oehler |
| 1989 | An algorithm for voice and data integration on packet-switched local area networks. Christopher Bucci, Alexander Albicki |
| 1989 | An automatic test pattern generation program for large ASICs. Dick L. Liu, Rajesh Galivanche, Charlie C. Hsu |
| 1989 | An efficient approach to pseudo-exhaustive test generation for BIST design. Chien-In Henry Chen, Gerald E. Sobelman |
| 1989 | An enhanced high performance combinational fault simulator using two-way parallelism. Steven P. Smith |
| 1989 | An integrated floating point vector processor for DSP and scientific computing. D. Spaderna, P. Green, K. Tam, T. Datta, M. Kumar |
| 1989 | An integrated free space optical bus. Alex G. Dickinson, Michael E. Prise |
| 1989 | Architectural features of the i860(TM)-microprocessor RISC core and on-chip caches. Piyush Patel, Diane Douglass |
| 1989 | Automated synthesis of systems with interacting asynchronous (self-timed) and synchronous components. P. A. Subrahmanyam |
| 1989 | Automatic signal net-matching for VLSI layout design. Xiao-Ming Xiong, Dan Green, John Hardin, Lawrence Riedel |
| 1989 | Automatic verification of speed-independent circuits with Petri net specifications. David L. Dill, Steven M. Nowick, Robert F. Sproull |
| 1989 | BiCMOS, a technology for high-speed/high-density ICs. H. Klose, B. Zehner, A. Wieder |
| 1989 | Built-in test methodology for a full custom processor chip. Ravinder S. Shergill, Pak-Ho Yeung, Patrick A. Tucci |
| 1989 | Circuit technologies for BiCMOS VLSI's as computer elements. Hideo Maejima, Tadaaki Bandoh, Yoji Nishio, Tadashi Fukushima, Masanori Odaka, Atsuo Hotta |
| 1989 | Comparison of chip crossing delay in various packaging environments. Ravi Kaw |
| 1989 | Computation with simultaneously concurrent error detection using bi-directional operands. L. G. Chen, T. H. Chen |
| 1989 | Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989 |
| 1989 | Computer aided design and built in self test on the i486TM CPU. Pat Gelsinger, Sundar Iyengar, Joseph Krauskopf, James Nadir |
| 1989 | Computer aided design system for VLSI interconnections. Jerzy W. Rozenblit, John L. Prince, Olgierd A. Palusinski, T. D. Whipple |
| 1989 | Concurrent checking in dedicated controllers. Régis Leveugle, Gabriele Saucier |
| 1989 | Correctness verification of VLSI modules supported by a very efficient Boolean prover. P. Lammens, Luc J. M. Claesen, Hugo De Man |
| 1989 | Counter-based residue arithmetic circuit for easily testable VLSI digital signal processing systems. Nobuhiro Tomabechi |
| 1989 | DAGAR: an automatic pipelined microarchitecture synthesis system. Vijay K. Raj |
| 1989 | Design of TSC checkers for implementation in CMOS technology. Sandip Kundu, Sudhakar M. Reddy |
| 1989 | Design of sufficiently strongly self-checking embedded checkers for systematic and separable codes. Niraj K. Jha |
| 1989 | Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture. Yervant Zorian, Najmi Jarwala |
| 1989 | Digital and analog integrated-circuit design with built-in reliability. Wen-Jay Hsu, Bing J. Sheu, Vance C. Tyree |
| 1989 | Efficient double asymmetric error correcting codes. Nasir Darwish, Bella Bose |
| 1989 | Electromigration median time-to-failure based on a stochastic current waveform. Farid N. Najm, Ibrahim N. Hajj, Ping Yang |
| 1989 | Evolution in the application of ASICs in the second-generation Titan. Glen S. Miranker, Jon Rubinstein, John Sanguinetti |
| 1989 | FOCUS: an experimental environment for validation of fault-tolerant systems - case study of a jet-engine controller. Gwan Choi, Ravi K. Iyer, Victor Carreno |
| 1989 | FPC: a floating-point processor controller chip for systolic signal processing. Ross A. W. Smith, Gerald E. Sobelman, George Luk, Koichi Suda, Jeff Bracken |
| 1989 | Fast MOS circuit simulation with a direct equation solver. Y.-H. Shih, S. M. Kang |
| 1989 | Fault-tolerant VLSI processor array for the SVD. Joseph R. Cavallaro, Christopher D. Near, M. Ümit Uyar |
| 1989 | Floorplan optimization on multiprocessors. Sunil Arvindam, Vipin Kumar, V. Nageshwara Rao |
| 1989 | Formal verification of state-machines using higher-order logic. Paul Loewenstein |
| 1989 | Frigg: a simulation environment for multiple-processor DSP system development. Jeffrey C. Bier, Edward A. Lee |
| 1989 | Generic ASIC architecture for digital signal processing. Stewart G. Smith, Ralph W. Morgan, Julian G. Payne |
| 1989 | HYPER: an interactive synthesis environment for high performance real time applications. Chi-Min Chu, Miodrag Potkonjak, Markus Thaler, Jan M. Rabaey |
| 1989 | Hamming count-a compaction testing technique. Anita Gleason, Wen-Ben Jone |
| 1989 | High performance I/O processors for real-time pulse handling. Masayoshi Tachibana, Yoshihisa Kondo, Yasuo Yamada, Masafumi Takahashi, Haruyuki Tago |
| 1989 | High performance circuits for the i486TM processor. James Miller, Ben Roberts, Paul Madland |
| 1989 | High throughput reconstruction of Huffman-coded images. Horng-Dar Lin, David G. Messerschmitt |
| 1989 | IBM RISC chip design methodology. Paul Villarrubia, Gary Nusbaum, Robert Masleid, P. T. Patel |
| 1989 | IBM second-generation RISC machine organization. H. B. Bakoglu, Gregory F. Grohoski, L. E. Thatcher, James A. Kahle, Charles R. Moore, David P. Tuttle, Warren E. Maule, W. R. Hardell Jr., Dwain A. Hicks, M. Nguyenphu, Robert K. Montoye, W. T. Glover, Sudhir Dhawan |
| 1989 | Identification of undetectable faults in combinational circuits. Mohan Harihara, Prem R. Menon |
| 1989 | Impact of BiCMOS technology on SRAM circuit design. P. Kuen Fung, Hiep V. Tran, David B. Scott |
| 1989 | Improved testability evaluations in combinational logic networks. Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò |
| 1989 | Integrated optoelectronics-to-VLSI packaging technology. C. G. Lin-Hendel, W. J. Bertram, M. S. Dhanaliwala, R. J. Pimpinella, J. M. Segelken, King L. Tai |
| 1989 | Integration and packaging plateaus of processor performance. Norman P. Jouppi |
| 1989 | Intelligent backtracking in test generation for combinational circuits. W. B. Zeng, D. Z. Wei |
| 1989 | Internal ECL-BiCMOS translator circuits in half micron technology. Gerard Boudon, Frank Wallart, Eric Maillart |
| 1989 | Issues in the implementation of the i486TM cache and bus. Ed Grochowski, Ken Shoemaker |
| 1989 | Issues in the test of artificial neural networks. Frank Warkowski, Jens Leenstra, Jos Nijhuis, Lambert Spaanenburg |
| 1989 | Locality characteristics of symbolic programs. William C. Hobart Jr., Harvey G. Cragon |
| 1989 | Logic decomposition algorithms for the timing optimization of multi-level logic. Pierre G. Paulin, Franck J. Poirot |
| 1989 | Logic minimization for factored forms. Abdul A. Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1989 | Macrocell-level compaction with automatic jog introduction. Alexander Herrigel, J. Kamm, Wolfgang Fichtner |
| 1989 | Magnitude classes in switch-level modeling. Eduard Cerny, John P. Hayes, Nicholas C. Rumin |
| 1989 | Mind: a module binder for high level synthesis. Chia-Jeng Tseng, Steven G. Rothweiler, Shailesh Sutarwala, Ajit M. Prabhu |
| 1989 | Modeling timing assumptions with trace theory. Jerry R. Burch |
| 1989 | Motion estimation VLSI architecture for image coding. Gilles Privat, Marc Renaudin |
| 1989 | Multiple-valued Boolean minimization based on graph coloring. Maciej J. Ciesielski, Saeyang Yang, Marek A. Perkowski |
| 1989 | Novel architecture for a high performance full custom graphics processor. M. D. Asal, J. D. Keay, A. M. Fellows, I. C. Robertson, N. K. Ing-Simmons, I. J. Sherlock |
| 1989 | OPAM: an efficient output phase assignment for multilevel logic minimization. Chin-Long Wey, Sin-Min Chang, Jing-Yang Jou |
| 1989 | On a class of (2n-1)-stage rearrangeable interconnection networks. Calvin J. A. Hsia, C. Y. Roger Chen |
| 1989 | Optical interconnects for interprocessor communications in the Connection Machine. Brewster O. Kahle, Edward C. Parish, Thomas A. Lane, Jerry A. Quam |
| 1989 | Ordered binary decision diagrams and circuit structure. C. Leonard Berman |
| 1989 | Parallel-concurrent fault simulation. Daniel G. Saab, Ibrahim N. Hajj, Joseph T. Rahmeh |
| 1989 | Performance and microarchitecture of the i486TM processor. Beatrice Fu, Avtar Saini, Patrick P. Gelsinger |
| 1989 | Reliability issues of MOS and bipolar ICs. Chenming Hu |
| 1989 | SLAM: a smart analog module layout generator for mixed analog-digital VLSI design. David J. Chen, Ji-Chien Lee, Bing J. Sheu |
| 1989 | Scheduling unequal length tests in high performance VLSI system implementations. John Y. Sayah, Charles R. Kime |
| 1989 | Schematic specification of datapath layout. Donald Curry |
| 1989 | Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability. Yusuf Leblebici, Sung-Mo Kang |
| 1989 | System-level design verification in the AT&T Computer Division: tools. Miron Abramovici, James J. Kulikowski, David T. Miller, Prem R. Menon |
| 1989 | System-level design verification in the AT&T computer division: overview and strategy. Miron Abramovici, J. W. Bierbauer, R. H. Hellman, C. L. Hong, David T. Miller, R. G. Taylor |
| 1989 | Systolic L-U decomposition array with a new reciprocal cell. Vijay K. Jain, David L. Landis, C. E. Alvarez |
| 1989 | Systolic implementation of neural networks. Mohammad Zubair, B. B. Madan |
| 1989 | Testability of digital circuits via the spectral domain. Brian R. Bannister, David R. Melton, Gaynor E. Taylor |
| 1989 | The bus interface and paging units of the i860TM microprocessor. Michael W. Rhodehamel |
| 1989 | The channel intersection problem in the building block style layout. Pierre-François Dubois |
| 1989 | The design and implementation of a multi-queue buffer for VLSI communication switches. Gregory L. Frazier, Yuval Tamir |
| 1989 | The design of a multi-chip single package digital signal processing module. C. G. Lin-Hendel, L. H. Cong |
| 1989 | The matrix transform chip. Sailesh K. Rao |
| 1989 | The role of synthesis in an ASIC design environment. Jeffrey R. Fox, Douglas Pastorello |
| 1989 | Verifying pipelined hardware using symbolic logic simulation. Soumitra Bose, Allan L. Fisher |