ICCD C

125 papers

YearTitle / Authors
1988A GaAs vector memory system for signal processing.
T. A. Misko
1988A class of fault-tolerant cellular permutation networks.
Mohsine Eleuldj, El Mostapha Aboulhamid, Eduard Cerny
1988A co-processor with supercomputer capabilities for personal computers.
W. Marwood, A. P. Clarke
1988A comparison of two digit serial VLSI adders.
Mary Jane Irwin, Robert Michael Owens
1988A functional approach to formal hardware verification: the MTI experience.
Dominique Borrione, Paolo Camurati, J. L. Paillet, Paolo Prinetto
1988A global chip test implementation including built-in self-test.
A. C. Erdal, Pierre A. Uszynski
1988A high performance CMOS chipset for FFT processors.
Shannon Shen, Surendar Magar, Raul Aguilar, Gerry Luikuo, Mike Fleming, K. Rishavy, K. Murphy, C. Furman
1988A high speed static CMOS PLA architecture.
William E. Engeler, Menahem Lowy, John Pedicone, John Bloomer, James Richotte, David Chan
1988A higher level hardware design verification.
Atsushi Takahara, Takashi Nanya
1988A highly parallel processor with an instruction set including relational algebra.
Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec
1988A matched-delay CMOS TDM multiplexer cell.
Charles A. Zukowski, Kevin Shum
1988A methodology for the control and custom VLSI implementation of large-scale Clos networks.
J. Robert Heath, Eric Allen Disch
1988A modular VLSI architecture for coincidence detection in positron emission tomography.
Danny F. Newport, H. M. Dent, M. E. Casey, Donald W. Bouldin
1988A modular scan-based testability system.
Franc Brglez, David Bryan, John D. Calhoun, Robert Lisanke
1988A new class of symmetric error correcting / unidirectional error detecting codes.
Niraj K. Jha
1988A novel VLSI architecture for the real-time implementation of 2-D signal processing systems.
Seong-Mo Park, Winser E. Alexander, Jung H. Kim, William E. Batchelor, William T. Krakow
1988A novel approach to the synthesis of practical datapath architectures using artificial intelligence techniques.
N. S. H. Brooks, R. J. Mack
1988A parallel simulated annealing algorithm for channel routing on a hypercube multiprocessor.
Randall J. Brouwer, Prithviraj Banerjee
1988A proposed standard test bus and boundary scan architecture.
Lee Whetsel
1988A rule based logic reorganization system LORES/EX.
J. Ishikawa, H. Sato, M. Hiramine, Kasumi Ishida, S. Oguri, Y. Kazuma, S. Murai
1988A self-reconfiguration scheme for fault-tolerant VLSI processor arrays.
Stephen Pateras, Janusz Rajski
1988A serial-input serial-output bit-sliced convolver.
Luigi Dadda, Luca Breveglieri
1988A testable PLA design with low overhead and ease of test generation.
Jing-Yang Jou
1988APES: an integrated system for behavioral design, simulation and evaluation of array processors.
Fausto Distante, Vincenzo Piuri
1988Adaptative backtrace and dynamic partitioning enhance ATPG.
Antonio Lioy
1988Aliasing errors in signature analysis testing of integrated circuits.
Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò
1988Alternative strategies for applying min-cut to VLSI placement.
Dwight D. Hill
1988An octagonal geometry compactor.
Paul K. Sun
1988Analog circuit synthesis and exploration in OASYS.
Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
1988Approaching a nanosecond: a 32 bit adder.
Gary Bewick, Paul Song, Giovanni De Micheli, Michael J. Flynn
1988Area evaluation metrics for transistor placement.
Tom Shiple, Paul Kollaritsch, Derek Smith, Jonathan Allen
1988Array partitioning: a methodology for reconfigurability and reconfiguration problems.
Fausto Distante, Fabrizio Lombardi, Donatella Sciuto
1988Automatic layout and optimization of static CMOS cells.
Frédéric Mailhot, Giovanni De Micheli
1988CESAR - A programmable high performance systolic array processor.
Morten Toverud, Vidar Andersen
1988CREATE-LIFE: a design system for high performances VLSI circuits.
Junien Labrousse, Gerrit A. Slavenburg
1988CTP-A family of optimizing compilers for the NS32532 microprocessor.
Chaim Bendelac, Gady Erlich
1988Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor.
Tadahiko Nishimukai, Hideo Inayoshi, Kikuko Takagi, Kazuhiko Iwasaki, Ikuya Kawasaki, M. Hanawa, Takeshi Okada
1988Classical fault analysis for MOS VLSI circuits.
Brian L. Shing, Mark A. Franklin
1988Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization.
P. Sadayappan, V. Visvanathan
1988Compilation of communicating processes into delay-insensitive circuits.
Kees van Berkel, Ronald W. J. J. Saeijs
1988Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988
1988Computer-aided simulation of optical interconnects for high-speed digital systems.
Andrew T. Yang, D. S. Gao, S. M. Kang
1988Critic: a knowledge-based program for critiquing circuit designs.
Rick L. Spickelmier, A. Richard Newton
1988Current sensing for built-in testing of CMOS circuits.
Derek B. I. Feltham, Phil Nigh, L. Richard Carley, Wojciech Maly
1988Design of a 20 MHz 64-tap transversal filter.
Chip C. Stearns, Daniel Luthi, Peter A. Ruetz, Peng H. Ang
1988Design of a 64-processor by 128-memory crossbar switching network.
Robert F. Miracky, A. Hartmann, L. N. Smith, S. Redfield, U. Ghoshal, B. Weigler
1988Design of a high-speed arithmetic datapath.
Mark Birman, George Chu, Larry Hu, John McLeod, N. Bedard, F. Ware, L. Torban, C. M. Lim
1988Design tradeoffs for a 40 MIPS (peak) CMOS 32-bit microprocessor.
D. K. Lewis, J. P. Costello, D. M. O'Connor
1988Direct synthesis of mapping circuits.
Liliana Díaz-Olavarrieta, Safwat G. Zaky
1988ES/3090: a realization of ESA/370 system architecture in IBM's most powerful mainframe computer through a balance of technology and system innovations.
William J. Nohilly
1988EXIST: an interactive VLSI architectural environment.
Pieter S. van der Meulen, Ming-Der Huang, Uzi Bar-Gadda, Eva Lee, Peter G. M. Baltus
1988Error tolerance in parallel simulated annealing techniques.
Rajeev Jayaraman, Frederica Darema
1988Estimation of area and performance overheads for testable VLSI circuits.
J. R. Miles, Anthony P. Ambler, K. A. E. Totton
1988Extension of a transistor level digital timing simulator to include first order analog behavior.
Rakesh Chadha, Chin-Fu Chen
1988Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellor.
Melvin A. Breuer, Amitava Majumdar, Cauligi S. Raghavendra
1988First 32-bit SPARC-based processors implemented in high-speed CMOS.
Masood Namjoo
1988Floating point CORDIC for matrix computations.
Joseph R. Cavallaro, Franklin T. Luk
1988Free-space optical crossover interconnects for parallel computers.
Jürgen Jahns
1988Gate array technology.
Conrad J. Dell'Oca
1988Generation of high speed CMOS multiplier-accumulators.
King Fai Pang, Hsui-Wei Soong, Randal Sexton, Peng-Huat Ang
1988HIT: a standard constructional system for testability and maintainability.
Brian R. Wilkins
1988High speed, low power CMOS transmitter-receiver system.
Thaddeus J. Gabara, David W. Thompson
1988IEEE P1149 Proposed Standard Testability Bus - An update with case histories.
Jon Turino
1988Implementation of fast radix-4 division with operands scaling.
Milos D. Ercegovac, Tomás Lang, Ramin Modiri
1988Instruction reorganization for a variable-length pipelined microprocessor.
Seth Abraham, Krishnan Padmanabhan
1988Integrated design and test synthesis.
Catherine H. Gebotys, Mohamed I. Elmasry
1988Interconnection delay in very high-speed VLSI.
D. Zhou, Franco P. Preparata, S. M. Kang
1988Knowledge-based analog circuit synthesis with flexible architecture.
Antony H. Fung, David J. Chen, Ying-Nan Lai, Bing J. Sheu
1988Large memory embedded ASICs.
Tetsuya Iizuka, Takayasu Sakurai, J. Matsunaga, K. Maeguchi, K. Kawagai, T. Kobayashi, Y. Shiotari, K. Kobayashi, T. Miyoshi
1988Limits of backplane bus design.
Paul L. Borrill
1988MILES: a mixed level simulator for analog/digital design.
A. C. J. Stroucken, G. J. J. M. van de Ven
1988Mapping properties of multi-level logic synthesis operations.
Mario C. Lega
1988McMAP: a fast technology mapping procedure for multi-level logic synthesis.
Robert Lisanke, Franc Brglez, Gershon Kedem
1988Microarchitecture of the 80960 high-integration processors.
Glenn Hinton, Konrad Lai, Randy Steck
1988Modeling and simulation of coupled lossy lines for VLSI interconnections.
Olgierd A. Palusinski, Andreas C. Cangellaris, John L. Prince, J. C. Liao, L. Vakanis
1988Multi-chip packaging for high performance systems.
Clinton C. Chao, Kim H. Chen, Ravi Kaw, Jacques Leibovitz, V. K. Nagesh, Kenneth D. Scholz
1988Object relocation in OX.
James H. Kukula
1988On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors.
S. H. Hosseini
1988Optimization for automatic cell assembly.
D. P. Dutt, G. Lakhani
1988PARET: an integrated visual tool for the study of parallel systems.
Kathleen M. Nichols, John T. Edmark
1988PLA based finite state machines using Johnson counters as state memories.
Rainer Amann, Bernhard Eschermann, Utz G. Baitinger
1988Parallel LU factorization for circuit simulation on an MIMD computer.
Chien-Chih Chen, Yu-Hen Hu
1988Parallel calculation of shortest paths in sparse graphs on a systolic array.
Sabine Bauer, Uwe Schwiegelshohn
1988Parallel decomposition of multipliers modulo (2
Alexander Skavantzos, Fred J. Taylor
1988Potential applications of high-T
Mehdi Hatamian, Larry A. Hornak, Stuart K. Tewksbury
1988Processor design using path programmable logic.
J. Kelly Flanagan, Brent E. Nelson
1988Proof and synthesis.
Michael P. Fourman, W. J. Palmer, R. M. Zimmer
1988RISC architecture of the M88000.
Charles Melear
1988Random testability analysis: comparing and evaluating existing approaches.
Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda
1988Reconfiguration strategies in VLSI processor arrays.
Krishna P. Belkhale, Prith Banerjee
1988Representation of control and timing behavior with applications to interface synthesis.
Sally A. Hayati, Alice C. Parker, John J. Granacki
1988SID: synthesis of integral design.
Donald F. Hooper Jr.
1988Set-associative dynamic random access memory.
Stephen A. Ward, Robert C. Zak
1988Simulated annealing on a multiprocessor.
Roger D. Chamberlain, Mark N. Edelman, Mark A. Franklin, Ellen E. Witte
1988Sorting on an array of processors.
H. V. Jagadish
1988Stop criteria in simulated annealing.
Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken
1988Super computer technology at Convex.
Harold Dozier, Jeff Gruger
1988Synthesis from VHDL.
Joseph Lis, Daniel D. Gajski
1988System interface of the NS32532 microprocessor.
Sidi Yom Tov, Benjamin Maytal, Z. Bikovsky, Dan Biran, Jonathan Levy II, Y. Milstain, A. Ostrer
1988Tera-Hertz study of normal and superconducting transmission lines.
C. C. Chi, D. Grischkowsky
1988Test generation by fault sampling.
Vishwani D. Agrawal, Hassan Farhat, Sharad Seth
1988Test generation in a parallel processing environment.
Susheel J. Chandra, Janak H. Patel
1988Test generation of C-testable array dividers.
Chin-Long Wey, Sin-Min Chang
1988Testing of VLSI regular arrays.
William P. Marnane, Will R. Moore
1988The Astronautics ZS-1 processor.
James E. Smith, Gregory E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James Laudon
1988The BACK algorithm for sequential test generation.
Wu-Tung Cheng
1988The Cray Y-MP-a VLSI supercomputer.
Stephen A. Bowen
1988The CydraTM 5 computer system architecture.
Michael Schlansker, Michael McNamara
1988The KARL/KARATE system - integrating functional test development into a CAD environment for VLSI.
Gerold Alfs, Reiner W. Hartenstein, Andrea Wodtko
1988The MIPS M2000 system.
Tom Riordan, G. P. Grewal, Simon Hsu, John Kinsel, Jeff Libby, Roger March, Marvin Mills, Paul Ries, Randy Scofield
1988The POTATO chip architecture: a study in tradeoffs for signal processing chip design.
B. Sharma, Rajiv Jain, Melvin A. Breuer, Alice C. Parker, Cauligi S. Raghavendra, C. Y. Tseng
1988The capability mechanism of a VLSI processor.
Kanad Ghose, Robert M. Stewart Jr.
1988The design of a reduced ambient temperature, air cooled supercomputer.
Donald R. Mullen, Geoffrey Fernald
1988The design of the VLSI image-generator ZaP.
Ronald W. J. J. Saeijs, Kees van Berkel
1988Trace driven modelling and performance evaluation of tightly coupled multiprocessor systems.
Khai-Quang Luc, Shauchi Ong, Elbert C. Hu
1988Transient fault behavior in a microprocessor - A case study.
P. Duba, Ravi K. Iyer
1988UBIST version of the SYCO's control section compiler.
Kholdoun Torki, Michael Nicolaidis, Ahmed Amine Jerraya, Bernard Courtois
1988Use of redundant binary representation for fault-tolerant arithmetic array processors.
Vincenzo Piuri, Renato Stefanelli
1988VITAL: fully automatic placement strategies for very large semicustom designs.
Rathin Putatunda, David Smith, Michael Stebnisky, Carl Puschak, Paul Patent
1988VLSI implementation of GSC architecture with a new ripple carry adder.
Irving S. Reed, B. Sharma, Ming-Tang Shih, John Bailey, Trieu-Kien Truong
1988VLSI programming and silicon compilation; a novel approach from Philips research.
Cees Niessen, Kees van Berkel, Martin Rem, Ronald W. J. J. Saeijs
1988VLSI programming.
Kees van Berkel, Martin Rem, Ronald W. J. J. Saeijs
1988VLSI support for copyback caching protocols on Futurebus.
Paul Sweazey
1988Variable reduction in MOS timing models.
Charles A. Zukowski, De-Ping Chen
1988Verifiable and executable theories of design for synthesizing correct hardware.
Shiu-Kai Chin, Kevin J. Greene