ICCAD A

146 papers

YearTitle / Authors
20062006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006
Soha Hassoun
2006A bitmask-based code compression technique for embedded systems.
Seok-Won Seong, Prabhat Mishra
2006A code refinement methodology for performance-improved synthesis from C.
Greg Stitt, Frank Vahid, Walid A. Najjar
2006A delay fault model for at-speed fault simulation and test generation.
Irith Pomeranz, Sudhakar M. Reddy
2006A fast block structure preserving model order reduction for inverse inductance circuits.
Hao Yu, Yiyu Shi, Lei He, David Smart
2006A framework for statistical timing analysis using non-linear delay and slew models.
Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula
2006A gate delay model focusing on current fluctuation over wide-range of process and environmental variability.
Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye
2006A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects.
Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner
2006A high-quality mixed-size analytical placer considering preplaced blocks and density constraints.
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
2006A linear-time approach for static timing analysis covering all process corners.
Sari Onaissi, Farid N. Najm
2006A network-flow approach to timing-driven incremental placement for ASICs.
Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar
2006A new RLC buffer insertion algorithm.
Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li, Weiping Shi
2006A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2006A new statistical max operation for propagating skewness in statistical timing analysis.
Kaviraj Chopra, Bo Zhai, David T. Blaauw, Dennis Sylvester
2006A novel framework for faster-than-at-speed delay test considering IR-drop effects.
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
2006A revisit to floorplan optimization by Lagrangian relaxation.
Chuan Lin, Hai Zhou, Chris C. N. Chu
2006A spectrally accurate integral equation solver for molecular surface electrostatics.
Shih-Hsien Kuo, Jacob White
2006A statistical framework for post-silicon tuning through body bias clustering.
Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw
2006A timing dependent power estimation framework considering coupling.
Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou
2006A unified non-rectangular device and circuit simulation model for timing and power.
Sean X. Shi, Peng Yu, David Z. Pan
2006Accelerating high-level bounded model checking.
Malay K. Ganai, Aarti Gupta
2006Adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and design.
Yonghong Yang, Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick
2006Algorithms for MIS vector generation and pruning.
Kenneth S. Stevens, Florentin Dartu
2006Allocation cost minimization for periodic hard real-time tasks in energy-constrained DVS systems.
Jian-Jia Chen, Tei-Wei Kuo
2006An accurate sparse matrix based framework for statistical static timing analysis.
Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
2006An adaptive two-level management for the flash translation layer in embedded systems.
Chin-Hsien Wu, Tei-Wei Kuo
2006An analytical model for negative bias temperature instability.
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
2006An efficient technique for synthesis and optimization of polynomials in GF(2
Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew
2006An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management.
Sheng-Chih Lin, Kaustav Banerjee
2006An optimal simultaneous diode/jumper insertion algorithm for antenna fixing.
Zhe-Wei Jiang, Yao-Wen Chang
2006Analog placement with symmetry and other placement constraints.
Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu
2006Analysis and modeling of CD variation for statistical static timing.
Brian Cline, Kaviraj Chopra, David T. Blaauw, Yu Cao
2006Analytical modeling of SRAM dynamic stability.
Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky
2006Application-independent defect-tolerant crossbar nano-architectures.
Mehdi Baradaran Tahoori
2006Application-specific customization of parameterized FPGA soft-core processors.
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen
2006Automatic memory reductions for RTL model verification.
Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon
2006Automation in mixed-signal design: challenges and solutions in the wake of the nano era.
Trent McConaghy, Georges G. E. Gielen
2006CMOS-MEMS integration: why, how and what?
Ann Witvrouw
2006Cache miss clustering for banked memory systems.
Ozcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy
2006Carbon nanotube transistor circuits: models and tools for design and performance optimization.
H.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan
2006Carbon nanotubes for potential electronic and optoelectronic applications.
Jia Chen
2006Clock buffer polarity assignment for power noise reduction.
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
2006Combinatorial algorithms for fast clock mesh optimization.
Ganesh Venkataraman, Zhuo Feng, Jiang Hu, Peng Li
2006Conjoining soft-core FPGA processors.
David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky
2006Cost-aware synthesis of asynchronous circuits based on partial acknowledgement.
Yu Zhou, Danil Sokolov, Alexandre Yakovlev
2006Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens.
Manoj Ampalam, Montek Singh
2006Current path analysis for electrostatic discharge protection.
Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Wei-Ting Tu, Chih-Hung Liu, Yao-Wen Chang, Sy-Yen Kuo
2006Decomposing image computation for symbolic reachability analysis using control flow information.
David Ward, Fabio Somenzi
2006Decoupling capacitor planning and sizing for noise and leakage reduction.
Eric Wong, Jacob R. Minz, Sung Kyu Lim
2006Design and CAD challenges in 45nm CMOS and beyond.
David J. Frank, Ruchir Puri, Dorel Toma
2006Design and integration methods for a multi-threaded dual core 65nm Xeon® processor.
Raj Varada, Mysore Sriram, Kris Chou, James Guzzo
2006Design automation for analog: the next generation of tool challenges.
Rob A. Rutenbar
2006Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques.
Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
2006Designing application-specific networks on chips with floorplan information.
Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
2006Dynamic power management using machine learning.
Gaurav Dhiman, Tajana Simunic Rosing
2006Dynamic voltage and frequency management based on variable update intervals for frequency setting.
Mehrdad Najibi, Mostafa E. Salehi, Ali Afzali-Kusha, Massoud Pedram, Seid Mehdi Fakhraie, Hossein Pedram
2006Efficient Boolean characteristic function for fast timed ATPG.
Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang
2006Efficient process-hotspot detection using range pattern matching.
Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai
2006Energy budgeting for battery-powered sensors with a known task schedule.
Daler N. Rakhmatov
2006Energy management for real-time embedded systems with reliability requirements.
Dakai Zhu, Hakan Aydin
2006Enhanced error vector magnitude (EVM) measurements for testing WLAN transceivers.
Erkan Acar, Sule Ozev, Kevin B. Redmond
2006Exploiting soft redundancy for error-resilient on-chip memory design.
Shuo Wang, Lei Wang
2006Exploring linear structures of critical path delay faults to reduce test efforts.
Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou
2006Factor cuts.
Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton
2006Fast and accurate transaction level models using result oriented modeling.
Gunar Schirner, Rainer Dömer
2006Fast and robust quadratic placement combined with an exact linear net model.
Peter Spindler, Frank M. Johannes
2006Fast decap allocation based on algebraic multigrid.
Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
2006Fast wire length estimation by net bundling for block placement.
Tan Yan, Hiroshi Murata
2006FastRoute: a step to integrate global routing into placement.
Min Pan, Chris C. N. Chu
2006Faster, parametric trajectory-based macromodels via localized linear reductions.
Saurabh K. Tiwary, Rob A. Rutenbar
2006Fill for shallow trench isolation CMP.
Andrew B. Kahng, Puneet Sharma, Alexander Zelikovsky
2006Formal model of data reuse analysis for hierarchical memory organizations.
Ilie I. Luican, Hongwei Zhu, Florin Balasa
2006From micro to nano: MEMS as an interface to the nano world.
Bernhard E. Boser
2006From molecular interactions to gates: a systematic approach.
Josep Carmona, Jordi Cortadella, Yousuke Takada, Ferdinand Peper
2006From single core to multi-core: preparing for a new exponential.
Jeff Parkhurst, John A. Darringer, Bill Grundmann
2006Fullwave volumetric Maxwell solver using conduction modes.
Salvador Ortiz, Roberto Suaya
2006Guaranteeing performance yield in high-level synthesis.
Wei-Lun Hung, Xiaoxia Wu, Yuan Xie
2006Handling inductance in early power grid verification.
Nahi H. Abdul Ghani, Farid N. Najm
2006High-level synthesis challenges and solutions for a dynamically reconfigurable processor.
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing
2006Importance of volume discretization of single and coupled interconnects.
Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail
2006Improvements to combinational equivalence checking.
Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén
2006Information processing in nanoscale arrays: DNA assembly, molecular devices, nano-array architectures.
Richard A. Kiehl
2006Information theoretic approach to address delay and reliability in long on-chip interconnects.
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
2006Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization.
Murari Mani, Ashish Kumar Singh, Michael Orshansky
2006Layer minimization of escape routing in area array packaging.
Renshen Wang, Rui Shi, Chung-Kuan Cheng
2006Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.
Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy
2006Leveraging protocol knowledge in slack matching.
Girish Venkataramani, Seth Copen Goldstein
2006Loop pipelining for high-throughput stream computation using self-timed rings.
Gennette Gill, John Hansen, Montek Singh
2006Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs.
Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
2006Microarchitecture parameter selection to optimize system performance under process variation.
Xiaoyao Liang, David M. Brooks
2006Molecular organic electronic circuits.
Vladimir Bulovic, Kyungbum Kevin Ryu, Charles G. Sodini, Ioannis Kymissis, Annie Wang, Ivan Nausieda, Akintunde Ibitayo Akinwande
2006Nanowire addressing with randomized-contact decoders.
Eric Rachlin, John E. Savage
2006Near-term industrial perspective of analog CAD.
Christopher Labrecque
2006Network coding for routability improvement in VLSI.
Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson
2006On bounding the delay of a critical path.
Leonard Lee, Li-C. Wang
2006On the use of Bloom filters for defect maps in nanocomputing.
Gang Wang, Wenrui Gong, Ryan Kastner
2006Online task-scheduling for fault-tolerant low-energy real-time systems.
Tongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang
2006Optimal memoryless encoding for low power off-chip data buses.
Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling
2006Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations.
Vaibhav Nawale, Thomas W. Chen
2006Optimizing yield in global routing.
Dirk Müller
2006Organic electronic device modeling at the nanoscale.
Conor F. Madigan, Vladimir Bulovic
2006PPV-HB: harmonic balance for oscillator/PLL phase macromodels.
Ting Mei, Jaijeet S. Roychowdhury
2006Performance analysis of concurrent systems with early evaluation.
Jorge Júlvez, Jordi Cortadella, Michael Kishinevsky
2006Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression.
Zhuo Feng, Peng Li
2006Performances improvement of FPGA using novel multilevel hierarchical interconnection structure.
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
2006Physical aware frequency selection for dynamic thermal management in multi-core systems.
Rajarshi Mukherjee, Seda Ogrenci Memik
2006Platform-based resource binding using a distributed register-file microarchitecture.
Jason Cong, Yiping Fan, Wei Jiang
2006Post-placement voltage island generation.
Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu
2006Post-routing redundant via insertion and line end extension with via density consideration.
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
2006Practical variation-aware interconnect delay and slew analysis for statistical timing verification.
Xiaoji Ye, Peng Li, Frank Liu
2006Precise identification of the worst-case voltage drop conditions in power grid verification.
Nestoras E. Evmorfopoulos, Dimitris P. Karampatzakis, Georgios I. Stamoulis
2006Prospects for emerging nanoelectronics in mainstream information processing systems.
Jeffrey Bokor
2006Robust estimation of parametric yield under limited descriptions of uncertainty.
Wei-Shen Wang, Michael Orshansky
2006Robust system level design with analog platforms.
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli
2006Runtime distribution-aware dynamic voltage scaling.
Sungpack Hong, Sungjoo Yoo, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo
2006SMT(
Hossein M. Sheini, Karem A. Sakallah
2006Simultaneous power and thermal integrity driven via stapling in 3D ICs.
Hao Yu, Joanna Ho, Lei He
2006Soft error derating computation in sequential circuits.
Hossein Asadi, Mehdi Baradaran Tahoori
2006Soft error reduction in combinational logic using gate resizing and flipflop selection.
Rajeev R. Rao, David T. Blaauw, Dennis Sylvester
2006Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search.
Zhaohui Fu, Sharad Malik
2006Stable and compact inductance modeling of 3-D interconnect structures.
Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh
2006State re-encoding for peak current minimization.
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
2006Stepping forward with interpolants in unbounded model checking.
Gianpiero Cabodi, Marco Murciano, Sergio Nocco, Stefano Quer
2006Studying a GALS FPGA architecture using a parameterized automatic design flow.
Xin Jia, Ranga Vemuri
2006System-level process-driven variability analysis for single and multiple voltage-frequency island systems.
Diana Marculescu, Siddharth Garg
2006System-wide energy minimization for real-time tasks: lower bound and approximation.
Xiliang Zhong, Cheng-Zhong Xu
2006TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation.
Xiaolue Lai, Jaijeet S. Roychowdhury
2006Technology migration techniques for simplified layouts with restrictive design rules.
Xiaoping Tang, Xin Yuan
2006Temperature-aware leakage minimization technique for real-time systems.
Lin Yuan, Sean Leventhal, Gang Qu
2006Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.
Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, Chuanjin Richard Shi
2006Testing delay faults in asynchronous handshake circuits.
Feng Shi, Yiorgos Makris
2006Thermal characterization and optimization in platform FPGAs.
Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan
2006Thermal sensor allocation and placement for reconfigurable systems.
Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci Memik
2006Thermal-induced leakage power optimization by redundant resource allocation.
Min Ni, Seda Ogrenci Memik
2006Timing model reduction for hierarchical timing analysis.
Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng
2006Timing-driven placement for heterogeneous field programmable gate array.
Bo Hu
2006Trunk decomposition based global routing optimization.
Devang Jariwala, John Lillis
2006UML for ESL design: basic principles, tools, and applications.
Wolfgang Mueller, Alberto Rosti, Sara Bocchio, Elvinia Riccobene, Patrizia Scandurra, Wim Dehaene, Yves Vanderperren
2006Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs.
Marvin Tom, David Leong, Guy G. Lemieux
2006Using CAD to shape experiments in molecular QCA.
Michael T. Niemier, Michael Crocker, Xiaobo Sharon Hu, Marya Lieberman
2006Variability and yield improvement: rules, models, and characterization.
Kenneth L. Shepard, Daniel N. Maynard
2006Verification of analog/mixed-signal circuits using labeled hybrid petri nets.
Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda
2006Verification through the principle of least astonishment.
Beth Isaksen, Valeria Bertacco
2006Voltage island aware floorplanning for power and timing optimization.
Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang
2006Wire density driven global routing for CMP variation and timing.
Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
2006Yield prediction for 3D capacitive interconnections.
Alberto Fazzi, Luca Magagni, Mario de Dominicis, Paolo Zoffoli, Roberto Canegallo, Pier Luigi Rolandi, Alberto L. Sangiovanni-Vincentelli, Roberto Guerrieri