| 2005 | 2005 International Conference on Computer-Aided Design, ICCAD 2005, San Jose, CA, USA, November 6-10, 2005 |
| 2005 | 2D data locality: definition, abstraction, and application. Mahmut T. Kandemir |
| 2005 | A cache-defect-aware code placement algorithm for improving the performance of processors. Tohru Ishihara, Farzan Fallah |
| 2005 | A cocktail approach on random access scan toward low power and high efficiency test. Krishnendu Chakrabarty, J. E. Chen |
| 2005 | A complete compositional reasoning framework for the efficient verification of pipelined machines. Panagiotis Manolios, Sudarshan K. Srinivasan |
| 2005 | A high efficiency full-chip thermal simulation algorithm. Yong Zhan, Sachin S. Sapatnekar |
| 2005 | A hybrid linear equation solver and its application in quadratic placement. Haifeng Qian, Sachin S. Sapatnekar |
| 2005 | A layout dependent full-chip copper electroplating topography model. Jianfeng Luo, Qing Su, Charles C. Chiang, Jamil Kawa |
| 2005 | A mapping algorithm for defect-tolerance of reconfigurable nano-architectures. Mehdi Baradaran Tahoori |
| 2005 | A more reliable reduction algorithm for behavioral model extraction. Dmitry Vasilyev, Jacob K. White |
| 2005 | A multi-harmonic probe technique for computing oscillator steady states. Kapil D. Boianapally, Ting Mei, Jaijeet S. Roychowdhury |
| 2005 | A routing algorithm for flip-chip design. Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang |
| 2005 | A sliding window scheme for accurate clock mesh analysis. Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai |
| 2005 | A statistical study of the effectiveness of BIST jitter measurement techniques. David Bordoley, Hieu Nguyen, Mani Soma |
| 2005 | A unified framework for statistical timing analysis with coupling and multiple input switching. Debjit Sinha, Hai Zhou |
| 2005 | Accurate delay computation for noisy waveform shapes. Amit Jain, David T. Blaauw, Vladimir Zolotov |
| 2005 | Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. Amit Agarwal, Kunhyuk Kang, Kaushik Roy |
| 2005 | Acyclic modeling of combinational loops. Amit Gupta, Charles Selvidge |
| 2005 | Adaptive designs for power and thermal optimization. Richard McGowen |
| 2005 | An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems. Ankur Agiwal, Montek Singh |
| 2005 | An automated technique for topology and route generation of application specific on-chip interconnection networks. Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod |
| 2005 | An efficient and effective detailed placement algorithm. Min Pan, Natarajan Viswanathan, Chris C. N. Chu |
| 2005 | An efficient and robust technique for tracking amplitude and frequency envelopes in oscillators. Ting Mei, Jaijeet S. Roychowdhury |
| 2005 | An efficient method for terminal reduction of interconnect circuits considering delay variations. Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He |
| 2005 | An escape routing framework for dense boards with high-speed design constraints. Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger |
| 2005 | An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. Paulo F. Flores, José Monteiro, Eduardo A. C. da Costa |
| 2005 | Application-specific network-on-chip architecture customization via long-range link insertion. Ümit Y. Ogras, Radu Marculescu |
| 2005 | Architecture and compilation for data bandwidth improvement in configurable embedded processors. Jason Cong, Guoling Han, Zhiru Zhang |
| 2005 | Architecture and details of a high quality, large-scale analytical placer. Andrew B. Kahng, Sherief Reda, Qinke Wang |
| 2005 | Automatic generalized phase abstraction for formal verification. Per Bjesse, James H. Kukula |
| 2005 | Battery optimization vs energy optimization: which to choose and when? Ravishankar Rao, Sarma B. K. Vrudhula |
| 2005 | Buffer insertion under process variations for delay minimization. Liang Deng, Martin D. F. Wong |
| 2005 | CDMA/FDMA-interconnects for future ULSI communications. M. Frank Chang |
| 2005 | Cellular wave computers and CNN technology - a SoC architecture with xK processors and sensor arrays. Tamás Roska |
| 2005 | Clustering for processing rate optimization. Chuan Lin, Jia Wang, Hai Zhou |
| 2005 | Code restructuring for improving cache performance of MPSoCs. Guilin Chen, Mahmut T. Kandemir |
| 2005 | Compiler-directed voltage scaling on communication links for reducing power consumption. Feihui Li, Guilin Chen, Mahmut T. Kandemir |
| 2005 | Complementary use of runtime validation and model checking. Ali Alphan Bayazit, Sharad Malik |
| 2005 | Computational geometry based placement migration. Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan |
| 2005 | Computer-aided design for DNA self-assembly: process and applications. Chris Dwyer |
| 2005 | ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing. Sanghamitra Roy, Weijen Chen |
| 2005 | Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. Martin K. F. Schafer, Thomas Hollstein, Heiko Zimmer, Manfred Glesner |
| 2005 | Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi |
| 2005 | Design automation issues for biofluidic microchips. Tamal Mukherjee |
| 2005 | Design of DNA origami. Paul W. K. Rothemund |
| 2005 | DiCER: distributed and cost-effective redundancy for variation tolerance. Di Wu, Ganesh Venkataraman, Jiang Hu, Quiyang Li, Rabi N. Mahapatra |
| 2005 | Digital RF processor (DRP™) for cellular phones. Robert Bogdan Staszewski, Khurram Muhammad, Dirk Leipold |
| 2005 | Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David T. Blaauw, Vladimir Zolotov |
| 2005 | Double-gate SOI devices for low-power and high-performance applications. Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici |
| 2005 | Dynamic voltage scaling for the schedulability of jitter-constrained real-time embedded systems. Bren Mochocki, Razvan Racu, Rolf Ernst |
| 2005 | Efficient LTL compilation for SAT-based model checking. Roy Armoni, Sergey Egorov, Ranan Fraer, Dmitry Korchemny, Moshe Y. Vardi |
| 2005 | Efficient algorithms for buffer insertion in general circuits based on network flow. Ruiming Chen, Hai Zhou |
| 2005 | Efficient analog platform characterization through analog constraint graphs. Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli |
| 2005 | Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen |
| 2005 | Eliminating wire crossings for molecular quantum-dot cellular automata implementation. Amitabh Chaudhary, Danny Z. Chen, Kevin Whitton, Michael T. Niemier, Ramprasad Ravichandran |
| 2005 | Embedded tutorial: formal equivalence checking between system-level models and RTL. Alfred Kölbl, Yuan Lu, Anmol Mathur |
| 2005 | Energy-efficient platform designs for real-world wireless sensing applications. Pai H. Chou, Chulsung Park |
| 2005 | Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra. Namrata Shekhar, Priyank Kalla, Florian Enescu, Sivaram Gopalakrishnan |
| 2005 | Expanding the frequency range of AWE via time shifting. Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail |
| 2005 | FPGA device and architecture evaluation considering process variations. Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He |
| 2005 | Fast algorithms for IR drop analysis in large power grid. Yu Zhong, Martin D. F. Wong |
| 2005 | Fast and efficient phase conflict detection and correction in standard-cell layouts. Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu |
| 2005 | Fast balanced stochastic truncation via a quadratic extension of the alternating direction implicit iteration. Ngai Wong, Venkataramanan Balakrishnan |
| 2005 | Fast thermal simulation for architecture level dynamic thermal management. Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang |
| 2005 | Fast timing closure by interconnect criticality driven delay relaxation. Love Singhal, Elaheh Bozorgzadeh |
| 2005 | Fast-yet-accurate PVT simulation by combined direct and iterative methods. Bo Hu, Chuanjin Richard Shi |
| 2005 | FastSies: a fast stochastic integral equation solver for modeling the rough surface effect. Zhenhai Zhu, Jacob K. White |
| 2005 | FinFETs for nanoscale CMOS digital integrated circuits. Tsu-Jae King |
| 2005 | Flip-flop insertion with shifted-phase clocks for FPGA power reduction. Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck Chang |
| 2005 | Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
| 2005 | Gate sizing using incremental parameterized statistical timing analysis. Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov |
| 2005 | Global signaling over lossy transmission lines. Michael P. Flynn, Joshua Jaeyoung Kang |
| 2005 | Hardware synthesis from guarded atomic actions with performance specifications. Daniel L. Rosenband |
| 2005 | Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. Anuradha Agarwal, Ranga Vemuri |
| 2005 | Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation. André DeHon, Konstantin Likharev |
| 2005 | IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin |
| 2005 | Improving scratch-pad memory reliability through compiler-guided data block duplication. Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ibrahim Kolcu |
| 2005 | Improving the efficiency of static timing analysis with false paths. Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris |
| 2005 | Incremental partitioning-based vectorless power grid verification. Dionysios Kouroussis, Imad A. Ferzli, Farid N. Najm |
| 2005 | Integrating loop and data optimizations for locality within a constraint network based framework. Guilin Chen, Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu |
| 2005 | Interval-valued statistical modeling of oxide chemical-mechanical polishing. James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning |
| 2005 | Intrinsic shortest path length: a new, accurate a priori wirelength estimator. Andrew B. Kahng, Sherief Reda |
| 2005 | Kauffman networks: analysis and applications. Elena Dubrova, Maxim Teslenko, Andrés Martinelli |
| 2005 | Memory access optimization of dynamic binary translation for reconfigurable architectures. Montek Singh |
| 2005 | Mixed-size placement via line search. Kristofer Vorwerk, Andrew A. Kennings |
| 2005 | New decompilation techniques for binary-level co-processor generation. Greg Stiff, Frank Vahid |
| 2005 | NoCEE: energy macro-model extraction methodology for network on chip routers. Jeremy Chan, Sri Parameswaran |
| 2005 | Noise margin analysis for dynamic logic circuits. Suwen Yang, Mark R. Greenstreet |
| 2005 | Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. Jaewon Seo, Taewhan Kim, Nikil D. Dutt |
| 2005 | Optimal routing algorithms for pin clusters in high-density multichip modules. Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger |
| 2005 | Oscillator-AC: restoring rigour to linearized small-signal analysis of oscillators. Ting Mei, Jaijeet S. Roychowdhury |
| 2005 | Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations. Xin Li, Peng Li, Lawrence T. Pileggi |
| 2005 | Parameterized model order reduction of nonlinear dynamical systems. Bradley N. Bond, Luca Daniel |
| 2005 | Parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitions. Erkan Acar, Sule Ozev |
| 2005 | Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David T. Blaauw, Dennis Sylvester |
| 2005 | Performance analysis of carbon nanotube interconnects for VLSI applications. Navin Srivastava, Kaustav Banerjee |
| 2005 | Performance-centering optimization for system-level analog design exploration. Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang |
| 2005 | Performance-driven read-after-write dependencies softening in high-level synthesis. Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida |
| 2005 | Pessimism reduction in crosstalk noise aware STA. Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh |
| 2005 | Physics-based compact modeling for nonclassical CMOS. Vishal P. Trivedi, Jerry G. Fossum, Leo Mathew, Murshed M. Chowdhury, Weimin Zhang, Glenn O. Workman, Bich-Yen Nguyen |
| 2005 | Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
| 2005 | Post-placement voltage island generation under performance requirement. Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang |
| 2005 | Post-verification debugging of hierarchical designs. Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler |
| 2005 | Power-aware microsensor design. Brian Schott, Michael Bajura |
| 2005 | Practical techniques to reduce skew and its variations in buffered clock networks. Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert |
| 2005 | Projection-based performance modeling for inter/intra-die variations. Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas |
| 2005 | RTL SAT simplification by Boolean and interval arithmetic reasoning. Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer |
| 2005 | Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance. Mosin Mondal, Yehia Massoud |
| 2005 | Reducing structural bias in technology mapping. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam |
| 2005 | Response shaper: a novel technique to enhance unknown tolerance for output response compaction. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng |
| 2005 | Robust automated synthesis methodology for integrated spiral inductors with variability. Arthur Nieuwoudt, Yehia Massoud |
| 2005 | Robust mixed-size placement under tight white-space constraints. Jason Cong, Michail Romesis, Joseph R. Shinnerl |
| 2005 | Runtime integrity checking for inter-object connections. Guilin Chen, Mahmut T. Kandemir |
| 2005 | SAT based solutions for consistency problems in formal property specifications for open systems. Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti |
| 2005 | SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill. Kwok-Shing Leung |
| 2005 | Scalable compositional minimization via static analysis. Fadi A. Zaraket, Jason Baumgartner, Adnan Aziz |
| 2005 | Serial-link bus: a low-power on-chip bus architecture. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De |
| 2005 | Simulation-based bug trace minimization with BMC-based refinement. Kai-Hui Chang, Valeria Bertacco, Igor L. Markov |
| 2005 | Static timing analysis considering power supply variations. Sanjay Pant, David T. Blaauw |
| 2005 | Statistical based link insertion for robust clock network design. Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen |
| 2005 | Statistical critical path analysis considering correlations. Yaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark |
| 2005 | Statistical gate sizing for timing yield optimization. Debjit Sinha, Narendra V. Shenoy, Hai Zhou |
| 2005 | Statistical technology mapping for parametric yield. Ashish Kumar Singh, Murari Mani, Michael Orshansky |
| 2005 | Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. Jeng-Liang Tsai, Lizheng Zhang |
| 2005 | Statistical timing analysis with two-sided constraints. Khaled R. Heloue, Farid N. Najm |
| 2005 | Steady-state analysis of voltage and current controlled oscillators. Amit Mehrotra, Suihua Lu, David C. Lee, Amit Narayan |
| 2005 | Storage assignment during high-level synthesis for configurable architectures. Wenrui Gong, Gang Wang, Ryan Kastner |
| 2005 | Synthesis methodology for built-in at-speed testing. Yinghua Li, Alex Kondratyev, Robert K. Brayton |
| 2005 | System level verification of digital signal processing applications based on the polynomial abstraction technique. Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch |
| 2005 | System software techniques for low-power operation in wireless sensor networks. Prabal Dutta, David E. Culler |
| 2005 | System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li |
| 2005 | TACO: temperature aware clock-tree optimization. Minsik Cho, Suhail Ahmed, David Z. Pan |
| 2005 | Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. Anuja Sehgal, Krishnendu Chakrabarty |
| 2005 | The circuit design of the synergistic processor element of a CELL processor. Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman |
| 2005 | The feasibility of on-chip interconnection using antennas. Kenneth K. O, Kihong Kim, Brian A. Floyd, Jesal Mehta, Hyun Yoon, Chih-Ming Hung, Daniel F. Bravo, Timothy O. Dickson, Xiaoling Guo, Ran Li, Narasimhan Trichy, James Caserta, Wayne R. Bomstad II, Jason Branch, Dong-Jun Yang, Jose L. Bohorquez, Jie Chen, Eunyoung Seok, Li Gao, Aravind Sugavanam, Jau-Jr Lin, S. Yu, Changhua Cao, M.-H. Hwang, Y.-R. Ding, S.-H. Hwang, Hsin-Ta Wu, N. Zhang, Joe E. Brewer |
| 2005 | The impact of the nanoscale on computing systems. Seth Copen Goldstein |
| 2005 | Thermal simulation techniques for nanoscale transistors. Jeremy A. Rowlette, Eric Pop, Sanjiv Sinha, Mathew Panzer, Kenneth E. Goodson |
| 2005 | Thermal via planning for 3-D ICs. Jason Cong, Yan Zhang |
| 2005 | Timing-aware power noise reduction in layout. Chao-Yang Yeh, Malgorzata Marek-Sadowska |
| 2005 | Total power-optimal pipelining and parallel processing under process variations in nanometer technology. Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge |
| 2005 | Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. Chuan Lin, Hai Zhou |
| 2005 | Transition-by-transition FSM traversal for reachability analysis in bounded model checking. Minh D. Nguyen, Dominik Stoffel, Markus Wedler, Wolfgang Kunz |
| 2005 | Variational analysis of large power grids by exploring statistical sampling sharing and spatial locality. Peng Li |
| 2005 | Verification of executable pipelined machines with bit-level interfaces. Panagiotis Manolios, Sudarshan K. Srinivasan |
| 2005 | Via-configurable routing architectures and fast design mappability estimation for regular fabrics. Yajun Ran, Malgorzata Marek-Sadowska |
| 2005 | Weighted control scheduling. Aravind Vijayakumar, Forrest Brewer |
| 2005 | Wirelength optimization by optimal block orientation. Xin Hao, Forrest Brewer |
| 2005 | Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara |