ICCAD A

118 papers

YearTitle / Authors
2002A Case for CMOS/nano co-design.
Matthew M. Ziegler, Mircea R. Stan
2002A Markov chain sequence generator for power macromodeling.
Xun Liu, Marios C. Papaefthymiou
2002A behavioral simulation tool for continuous-time delta sigma modulators.
Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen
2002A delay metric for RC circuits based on the Weibull distribution.
Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
2002A hierarchical modeling framework for on-chip communication architectures.
Xinping Zhu, Sharad Malik
2002A hybrid ASIC and FPGA architecture.
Paul S. Zuchowski, Christopher B. Reynolds, Richard J. Grupp, Shelly G. Davis, Brendan Cremen, Bill Troxel
2002A local circuit topology for inductive parasitics.
Andrea Pacelli
2002A new enhanced SPFD rewiring algorithm.
Jason Cong, Joey Y. Lin, Wangning Long
2002A novel framework for multilevel routing considering routability and performance.
Shih-Ping Lin, Yao-Wen Chang
2002A novel net weighting algorithm for timing-driven placement.
Tim (Tianming) Kong
2002A novel scan architecture for power-efficient, rapid test.
Ozgur Sinanoglu, Alex Orailoglu
2002A precorrected-FFT method for simulating on-chip inductance.
Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2002A realistic variable voltage scheduling model for real-time applications.
Bren Mochocki, Xiaobo Sharon Hu, Gang Quan
2002A technology-independent CAD tool for ESD protection device extraction: ESDExtractor.
Rouying Zhan, Haigang Feng, Qiong Wu, Guang Chen, Xiaokang Guan, Albert Z. Wang
2002ATPG-based logic synthesis: an overview.
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
2002An energy-conscious algorithm for memory port allocation.
Preeti Ranjan Panda, Lakshmikantam Chitturi
2002An enhanced multilevel routing system.
Jason Cong, Min Xie, Yan Zhang
2002Analog circuit sizing based on formal methods using affine arithmetic.
Andreas C. Lemke, Lars Hedrich, Erich Barke
2002Analysis and optimization of substrate noise coupling in single-chip RF transceiver design.
Adil Koukab, Kaustav Banerjee, Michel J. Declercq
2002Battery-aware power management based on Markovian decision processes.
Peng Rong, Massoud Pedram
2002Binary time-frame expansion.
Farzan Fallah
2002Bit-level scheduling of heterogeneous behavioural specifications.
María C. Molina, José M. Mendías, Román Hermida
2002CAD computation for manufacturability: can we save VLSI technology from itself?
Mark A. Lavin, Lars Liebmann
2002Characteristic faults and spectral information for logic BIST.
Xiaoding Chen, Michael S. Hsiao
2002Circuit power estimation using pattern recognition techniques.
Lipeng Cao
2002Combinational equivalence checking through function transformation.
Hee-Hwan Kwak, In-Ho Moon, James H. Kukula, Thomas R. Shiple
2002Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads.
Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David T. Blaauw
2002Comprehensive frequency-dependent substrate noise analysis using boundary element methods.
Hongmei Li, Jorge Carballido, Harry H. Yu, Vladimir I. Okhmatovski, Elyse Rosenbaum, Andreas C. Cangellaris
2002Concurrent flip-flop and repeater insertion for high performance integrated circuits.
Pasquale Cocchini
2002Conflict driven learning in a quantified Boolean Satisfiability solver.
Lintao Zhang, Sharad Malik
2002Conflict driven techniques for improving deterministic test pattern generation.
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
2002Congestion minimization during placement without estimation.
Bo Hu, Malgorzata Marek-Sadowska
2002Convertibility verification and converter synthesis: two faces of the same coin.
Roberto Passerone, Luca de Alfaro, Thomas A. Henzinger, Alberto L. Sangiovanni-Vincentelli
2002Coupling-aware high-level interconnect synthesis for low power.
Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
2002Design of pipeline analog-to-digital converters via geometric programming.
Maria del Mar Hershenson
2002Dynamic compilation for energy adaptation.
Priya Unnikrishnan, Guangyu Chen, Mahmut T. Kandemir, D. R. Mudgett
2002ECO algorithms for removing overlaps between power rails and signal wires.
Hua Xiang, Kai-Yuan Chao, D. F. Wong
2002Efficient crosstalk noise modeling using aggressor and tree reductions.
Li Ding, David T. Blaauw, Pinaki Mazumder
2002Efficient instruction encoding for automatic instruction set design of configurable ASIPs.
Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
2002Efficient mixed-domain analysis of electrostatic MEMS.
Gang Li, Narayan R. Aluru
2002Efficient model order reduction via multi-node moment matching.
Yehea I. Ismail
2002Efficient solution space exploration based on segment trees in analog placement with symmetry constraints.
Florin Balasa, Sarat C. Maruvada, Karthik Krishnamoorthy
2002Energy efficient address assignment through minimized memory row switching.
Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke
2002Estimation of signal arrival times in the presence of delay noise.
Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
2002Extraction and LVS for mixed-domain integrated MEMS layouts.
Bikram Baidya, Tamal Mukherjee
2002Fast methods for simulation of biomolecule electrostatics.
Shihhsien S. Kuo, Michael D. Altman, Jaydeep P. Bardhan, Bruce Tidor, Jacob K. White
2002Fast seed computation for reseeding shift register in test pattern compression.
Nahmsuk Oh, Rohit Kapur, Thomas W. Williams
2002FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materials.
Yehia Massoud, Jacob White
2002Folding of logic functions and its application to look up table compaction.
Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara
2002Frame-based dynamic voltage and frequency scaling for a MPEG decoder.
Kihwan Choi, Karthik Dantu, Wei-Chung Cheng, Massoud Pedram
2002Free space management for cut-based placement.
Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
2002GSTE through a case study.
Jin Yang, Amit Goel
2002Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step.
Hiran Tennakoon, Carl Sechen
2002General framework for removal of clock network pessimism.
Jindrich Zejda, Paul Frain
2002Generic ILP versus specialized 0-1 ILP: an update.
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
2002Hardware/software partitioning of software binaries.
Greg Stitt, Frank Vahid
2002High capacity and automatic functional extraction tool for industrial VLSI circuit designs.
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
2002High-level synthesis of distributed logic-memory architectures.
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2002INDUCTWISE: inductance-wise interconnect simulator and extractor.
Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie Chung-Ping Chen
2002Implicit treatment of substrate and power-ground losses in return-limited inductance extraction.
Dipak Sitaram, Yu Zheng, Kenneth L. Shepard
2002Incremental placement for layout driven optimizations on FPGAs.
Deshanand P. Singh, Stephen Dean Brown
2002Interconnect-aware high-level synthesis for low power.
Lin Zhong, Niraj K. Jha
2002Interface specification for reconfigurable components.
Satnam Singh
2002Layout-driven resource sharing in high-level synthesis.
Junhyung Um, Jae-Hoon Kim, Taewhan Kim
2002Leakage power modeling and reduction with data retention.
Weiping Liao, Joseph M. Basile, Lei He
2002Making Fourier-envelope simulation robust.
Jaijeet S. Roychowdhury
2002Managing power and performance for System-on-Chip designs using Voltage Islands.
David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn
2002Methods for true power minimization.
Robert W. Brodersen, Mark Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic
2002Metrics for structural logic synthesis.
Prabhakar Kudva, Andrew Sullivan, William E. Dougherty
2002Minimizing power across multiple technology and design levels.
Takayasu Sakurai
2002Molecular electronics: devices, systems and tools for gigagate, gigabit chips.
Michael Butts, André DeHon, Seth Copen Goldstein
2002Multi-objective circuit partitioning for cutsize and path-based delay minimization.
Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis
2002Noise propagation and failure criteria for VLSI designs.
Vladimir Zolotov, David T. Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy
2002Non-tree routing for reliability and yield improvement.
Andrew B. Kahng, Bao Liu, Ion I. Mandoiu
2002On mask layout partitioning for electron projection lithography.
Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong
2002On the difference between two widely publicized methods for analyzing oscillator phase behavior.
Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
2002On theoretical and practical considerations of path selection for delay fault testing.
Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng
2002On undetectable faults in partial scan circuits.
Irith Pomeranz, Sudhakar M. Reddy
2002On-chip interconnect modeling by wire duplication.
Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
2002Optimal buffered routing path constructions for single and multiple clock domain systems.
Soha Hassoun, Charles J. Alpert, Meera Thiagarajan
2002Optimization and control of
Tadahiro Kuroda
2002Optimization based passive constrained fitting.
Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira
2002Optimization of a fully integrated low power CMOS GPS receiver.
Peter J. Vancorenland, Philippe Coppejans, Wouter De Cock, Paul Leroux, Michiel Steyaert
2002Optimized power-delay curve generation for standard cell ICs.
Miodrag Vujkovic, Carl Sechen
2002Post global routing RLC crosstalk budgeting.
Jinjun Xiong, Jun Chen, James D. Z. Ma, Lei He
2002Power efficiency of voltage scaling in multiple clock, multiple voltage cores.
Anoop Iyer, Diana Marculescu
2002Predictability: definition, ananlysis and optimization.
Ankur Srivastava, Majid Sarrafzadeh
2002Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002
Lawrence T. Pileggi, Andreas Kuehlmann
2002Proximity templates for modeling of skin and proximity effects on packages and high frequency interconnect.
Luca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob K. White
2002Refining switching window by time slots for crosstalk noise calculation.
Pinhong Chen, Yuji Kukimoto, Kurt Keutzer
2002Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects.
Harshit K. Shah, Pun H. Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis
2002Resynthesis of multi-level circuits under tight constraints using symbolic optimization.
Victor N. Kravets, Karem A. Sakallah
2002Reversible logic circuit synthesis.
Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes
2002Robust and passive model order reduction for circuits containing susceptance elements.
Hui Zheng, Lawrence T. Pileggi
2002SAT and ATPG: Boolean engines for formal hardware verification.
Armin Biere, Wolfgang Kunz
2002Schedulability analysis of multiprocessor real-time applications with stochastic task execution times.
Sorin Manolache, Petru Eles, Zebo Peng
2002Schematic-based lumped parameterized behavioral modeling for suspended MEMS.
Qi Jing, Tamal Mukherjee, Gary K. Fedder
2002Shaping interconnect for uniform current density.
Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao
2002SiSMA: a statistical simulator for mismatch analysis of MOS ICs.
Giorgio Biagetti, Simone Orcioni, L. Signoracci, Claudio Turchetti, Paolo Crippa, Michele Alessandrini
2002Simplification of non-deterministic multi-valued networks.
Alan Mishchenko, Robert K. Brayton
2002Simplifying Boolean constraint solving for random simulation-vector generation.
Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
2002Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms.
Katarzyna Radecka, Zeljko Zilic
2002Standby power optimization via transistor sizing and dual threshold voltage assignment.
Mahesh Ketkar, Sachin S. Sapatnekar
2002Sub-90nm technologies: challenges and opportunities for CAD.
Tanay Karnik, Shekhar Borkar, Vivek De
2002Subthreshold leakage modeling and reduction techniques.
James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan
2002Symbolic pointer analysis.
Jianwen Zhu
2002Synthesis of custom processors based on extensible platforms.
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2002Synthesis of customized loop caches for core-based embedded systems.
Susan Cotterell, Frank Vahid
2002Test-model based hierarchical DFT synthesis.
Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, Felix Ng
2002The A to Z of SoCs.
Reinaldo A. Bergamaschi, John M. Cohn
2002Theoretical and practical validation of combined BEM/FEM substrate resistance modeling.
Eelco Schrik, Patrick M. Dewilde, N. P. van der Meijs
2002Throughput-driven IC communication fabric synthesis.
Tao Lin, Lawrence T. Pileggi
2002Timing-driven placement using design hierarchy guided constraint generation.
Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh
2002Topologically constrained logic synthesis.
Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
2002Track assignment: a desirable intermediate step between global routing and detailed routing.
Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou
2002Transmission line design of clock trees.
Rafael Escovar, Roberto Suaya
2002WTA: waveform-based timing analysis for deep submicron circuits.
Larry McMurchie, Carl Sechen
2002Whirlpool PLAs: a regular logic structure and their synthesis.
Fan Mo, Robert K. Brayton