| 2000 | A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions. Qiushuang Zhang, Ian G. Harris |
| 2000 | A Force-Directed Macro-Cell Placer. Fan Mo, Abdallah Tabbara, Robert K. Brayton |
| 2000 | A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis. Gernot Koch, Taewhan Kim, Reiner Genevriere |
| 2000 | A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits. Michael Pronath, Volker Gloeckel, Helmut E. Graeb |
| 2000 | A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. Jiang Hu, Sachin S. Sapatnekar |
| 2000 | A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy |
| 2000 | ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters. Erik Lauwers, Georges G. E. Gielen |
| 2000 | Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. Hans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan |
| 2000 | An "Effective" Capacitance Based Delay Metric for RC Interconnect. Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan |
| 2000 | An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays. Arlindo L. Oliveira, Rajeev Murgai |
| 2000 | Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering. Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas |
| 2000 | Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Submicron Technologies. Paul-Peter Sotiriadis, Anantha P. Chandrakasan |
| 2000 | Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method. Sungpack Hong, Taewhan Kim |
| 2000 | Challenges and Opportunities in Broadband and Wireless Communication Designs. Jan M. Rabaey, Miodrag Potkonjak, Farinaz Koushanfar, Suet-Fei Li, Tim Tuan |
| 2000 | Challenges in Physical Chip Design. Ralph H. J. M. Otten, Paul Stravers |
| 2000 | Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian Matrices. Alper Demir, David E. Long, Jaijeet S. Roychowdhury |
| 2000 | Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |
| 2000 | Counterexample-Guided Choice of Projections in Approximate Symbolic Model Checking. Shankar G. Govindaraju, David L. Dill |
| 2000 | Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang |
| 2000 | Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 2000 | DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators. Kenneth Francken, Peter J. Vancorenland, Georges G. E. Gielen |
| 2000 | DRAGON2000: Standard-Cell Placement Tool for Large Industry Circuits. Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh |
| 2000 | Data Path Placement with Regularity. Terry Tao Ye, Giovanni De Micheli |
| 2000 | Decomposing Refinement Proofs Using Assume-Guarantee Reasoning. Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani |
| 2000 | Delay Budgeting for a Timing-Closure-Driven Design Method. Chien-Chu Kuo, Allen C.-H. Wu |
| 2000 | Design-Manufacturing Interface for 0.13 Micron and Below. Andrzej J. Strojwas |
| 2000 | Deterministic Test Pattern Generation Techniques for Sequential Circuits. Ilker Hamzaoglu, Janak H. Patel |
| 2000 | Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. Ian G. Harris, Russell Tessier |
| 2000 | Don't Cares and Multi-Valued Logic Network Minimization. Yunjian Jiang, Robert K. Brayton |
| 2000 | Dynamic Response Time Optimization for SDF Graphs. Dirk Ziegenbein, Jan Uerpmann, Ralph Ernst |
| 2000 | Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views. Ke Zhong, Shantanu Dutt |
| 2000 | Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester |
| 2000 | Efficient Exploration of the SoC Communication Architecture Design Space. Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2000 | Efficient Finite-Difference Method for Quasi-Periodic Steady-State and Small Signal Analyses. Baolin Yang, Dan Feng |
| 2000 | Error Catch and Analysis for Semiconductor Memories Using March Tests. Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu |
| 2000 | Event Driven Simulation Without Loops or Conditionals. Peter M. Maurer |
| 2000 | Exploring Performance Tradeoffs for Clustered VLIW ASIPs. Margarida F. Jacome, Gustavo de Veciana, Viktor S. Lapinskii |
| 2000 | FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park |
| 2000 | Fast Analysis and Optimization of Power/Ground Networks. Haihua Su, Kaushik Gala, Sachin S. Sapatnekar |
| 2000 | Fast Test Application Technique Without Fast Scan Clocks. Seonki Kim, Bapiraju Vinnakota |
| 2000 | Frequency Domain Analysis of Switching Noise on Power Supply Network. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh |
| 2000 | Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction. Kenneth L. Shepard, Dipak Sitaram, Yu Zheng |
| 2000 | General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs. Hongbing Fan, Jiping Liu, Yu-Liang Wu |
| 2000 | Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling. Charlie Chung-Ping Chen, Tae-Woo Lee, Narayanan Murugesan, Susan C. Hagness |
| 2000 | Generalized Symmetries in Boolean Functions. Victor N. Kravets, Karem A. Sakallah |
| 2000 | Hierarchical Interconnect Circuit Models. Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi |
| 2000 | How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K. Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai |
| 2000 | Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees. Xiaodong Yang, Chung-Kuan Cheng, Walter H. Ku, Robert J. Carragher |
| 2000 | Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu |
| 2000 | Improving the Proportion of At-Speed Tests in Scan BIST. Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski |
| 2000 | Incremental CAD. Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh |
| 2000 | Latency Effects of System Level Power Management Algorithms. Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta |
| 2000 | Latency-Guided On-Chip Bus Network Design. Milenko Drinic, Darko Kirovski, Seapahn Meguerdichian, Miodrag Potkonjak |
| 2000 | Layout-Driven Area-Constrained Timing Optimization by Net Buffering. Rajeev Murgai |
| 2000 | MIST: An Algorithm for Memory Miss Traffic Management. Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
| 2000 | MONGREL: Hybrid Techniques for Standard Cell Placement. Sung-Woo Hur, John Lillis |
| 2000 | Miller Factor for Gate-Level Coupling Delay Calculation. Pinhong Chen, Desmond Kirkpatrick, Kurt Keutzer |
| 2000 | Modeling Non-Slicing Floorplans with Binary Trees. Florin Balasa |
| 2000 | Modelling and Analysis of Communication Circuit Performance Using Markov Chains and Efficient Graph Representations. Alper Demir, Peter Feldmann |
| 2000 | Multilevel Optimization for Large-Scale Circuit Placement. Tony F. Chan, Jason Cong, Tianming Kong, Joseph R. Shinnerl |
| 2000 | Noise Analysis of Phase-Locked Loops. Amit Mehrotra |
| 2000 | Observability Analysis of Embedded Software for Coverage-Directed Validation. José C. Costa, Srinivas Devadas, José Monteiro |
| 2000 | On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools. Andrew B. Kahng, Stefanus Mantik |
| 2000 | Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits. Sudip Chakrabarti, Abhijit Chatterjee |
| 2000 | Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng |
| 2000 | Physical Planning with Retiming. Jason Cong, Sung Kyu Lim |
| 2000 | Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm. Sangyun Kim, Peter A. Beerel |
| 2000 | Potential Slack: An Effective Metric of Combinational Circuit Performance. Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh |
| 2000 | Power Exploration for Embedded VLIW Architectures. Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria |
| 2000 | Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai |
| 2000 | Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. Jiong Luo, Niraj K. Jha |
| 2000 | Predictable Routing. Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh |
| 2000 | Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000 Ellen Sentovich |
| 2000 | Provably Good Global Buffering Using an Available Buffer Block Plan. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky |
| 2000 | Regularity Driven Logic Synthesis. Thomas Kutzschebauch, Leon Stok |
| 2000 | Simulation Based Test Generation for Scan Designs. Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | Simulation Coverage Enhancement Using Test Stimulus Transformations. C. Norris Ip |
| 2000 | Simulation and Optimization of the Power Distribution Network in VLSI Circuits. Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj |
| 2000 | Simultaneous Gate Sizing and Fanout Optimization. Wei Chen, Cheng-Ta Hsieh, Massoud Pedram |
| 2000 | Slope Propagation in Static Timing Analysis. David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda |
| 2000 | Smart Simulation Using Collaborative Formal and Simulation Engines. Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long |
| 2000 | Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes |
| 2000 | Switching Window Computation for Static Timing Analysis in Presence of Crosstalk Noise. Pinhong Chen, Desmond Kirkpatrick, Kurt Keutzer |
| 2000 | Symbolic Debugging Scheme for Optimized Hardware and Software. Farinaz Koushanfar, Darko Kirovski, Miodrag Potkonjak |
| 2000 | Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang |
| 2000 | Synthesis of Operation-Centric Hardware Descriptions. James C. Hoe, Arvind |
| 2000 | System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications. Lode Nachtergaele, Vivek Tiwari, Nikil D. Dutt |
| 2000 | Test Generation for Acyclic Sequential Circuits with Hold Registers. Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara |
| 2000 | Test of Future System-on-Chips. Yervant Zorian, Sujit Dey, Mike Rodgers |
| 2000 | Timing Driven Gate Duplication: Complexity Issues and Algorithms. Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh |
| 2000 | Transistor-Level Timing Analysis Using Embedded Simulation. Pawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin |
| 2000 | UST/DME: A Clock Tree Router for General Skew Constraints. Chung-Wen Albert Tsao, Cheng-Kok Koh |
| 2000 | Verification of Delta-Sigma Converters Using Adaptive Regression Modeling. Jeongjin Roh, Suresh Seshadri, Jacob A. Abraham |
| 2000 | Why Doesn't EDA Get Enough Respect? Andreas von Bechtolsheim, Joe Costello, Aart de Gues, Patrick Scaglia, Jennifer Smith |
| 2000 | Wire Reconnections Based on Implication Flow Graph. Shih-Chieh Chang, Zhong-Zhen Wu, He-Zhe Yu |