| 1996 | A coloring approach to the structural diagnosis of interconnects. Xiao-Tao Chen, Fabrizio Lombardi |
| 1996 | A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits. Luís Miguel Silveira, Mattan Kamon, Ibrahim M. Elfadel, Jacob White |
| 1996 | A design for testability technique for RTL circuits using control/data flow extraction. Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
| 1996 | A general dispersive multiconductor transmission line model for interconnect simulation in SPICE. Mustafa Celik, Andreas C. Cangellaris |
| 1996 | A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. Wen-Jong Fang, Allen C.-H. Wu |
| 1996 | A new method to express functional permissibilities for LUT based FPGAs and its applications. Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya |
| 1996 | A new method towards achieving global optimality in technology mapping. Xiaoqing Wen, Kewal K. Saluja |
| 1996 | A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects. Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben Song, Wayne Wei-Ming Dai |
| 1996 | A power modeling and characterization method for the CMOS standard cell library. Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou |
| 1996 | A video driver system designed using a top-down, constraint-driven methodology. Iasson Vassiliou, Henry Chang, Alper Demir, Edoardo Charbon, Paolo Miliozzi, Alberto L. Sangiovanni-Vincentelli |
| 1996 | ABILBO: Analog BuILt-in Block Observer. Marcelo Lubaszewski, Salvador Mir, Leandro Pulz |
| 1996 | ACV: an arithmetic circuit verifier. Yirng-An Chen, Randal E. Bryant |
| 1996 | Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. N. P. van der Meijs, T. Smedes |
| 1996 | Algorithms for address assignment in DSP code generation. Rainer Leupers, Peter Marwedel |
| 1996 | An algorithm for power estimation in switched-capacitor circuits. Chad Young, Giorgio Casinovi, Jonathan Fowler, Paul Kerstetter |
| 1996 | An algorithm for synthesis of system-level interface circuits. Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu |
| 1996 | An approximate timing analysis method for datapath circuits. Hakan Yalcin, John P. Hayes, Karem A. Sakallah |
| 1996 | An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data. Guowu Zheng, Qi-Jun Zhang, Michel S. Nakhla, Ramachandra Achar |
| 1996 | An efficient approach to simultaneous transistor and interconnect sizing. Jason Cong, Lei He |
| 1996 | An efficient, bus-layout based method for early diagnosis of bussed driver shorts in printed circuit boards. Kanad Chakraborty, Pinaki Mazumder |
| 1996 | An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |
| 1996 | An observability-based code coverage metric for functional simulation. Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer |
| 1996 | An optimal algorithm for river routing with crosstalk constraints. Hai Zhou, D. F. Wong |
| 1996 | Analytical delay models for VLSI interconnects under ramp input. Andrew B. Kahng, Kei Masuko, Sudhakar Muddu |
| 1996 | Automatic netlist extraction for measurement-based characterization of off-chip interconnect. Steven D. Corey, Andrew T. Yang |
| 1996 | Basic concepts for an HDL reverse engineering tool-set. Gunther Lehmann, Bernhard Wunder, Klaus D. Müller-Glaser |
| 1996 | Bit-flipping BIST. Hans-Joachim Wunderlich, Gundolf Kiefer |
| 1996 | Buffered Steiner tree construction with wire sizing for interconnect layout optimization. Takumi Okamoto, Jason Cong |
| 1996 | CTL model checking based on forward state traversal. Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose |
| 1996 | Clock skew optimization for ground bounce control. Ashok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska |
| 1996 | Clock tree synthesis for multi-chip modules. Daksh Lehther, Sachin S. Sapatnekar |
| 1996 | Clock-driven performance optimization in interactive behavioral synthesis. Hsiao-Ping Juan, Daniel Gajski, Viraphol Chaiyakul |
| 1996 | Compact and complete test set generation for multiple stuck-faults. Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Comparing models of computation. Edward A. Lee, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Computation of circuit waveform envelopes using an efficient, matrix-decomposed harmonic balance algorithm. Peter Feldmann, Jaijeet S. Roychowdhury |
| 1996 | Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults. Mukund Sivaraman, Andrzej J. Strojwas |
| 1996 | Design for manufacturability in submicron domain. Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag |
| 1996 | Design of robust test criteria in analog testing. Walter M. Lindermeir |
| 1996 | Digital sensitivity: predicting signal interaction using functional analysis. Desmond Kirkpatrick, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Directional bias and non-uniformity in FPGA global routing architectures. Vaughn Betz, Jonathan Rose |
| 1996 | Driving toward higher IDDQ test quality for sequential circuits: a generalized fault model and its ATPG. Hisashi Kondo, Kwang-Ting Cheng |
| 1996 | Efficient solution of systems of Boolean equations. Scott Woods, Giorgio Casinovi |
| 1996 | Efficient time-domain simulation of frequency-dependent elements. Sharad Kapur, David E. Long, Jaijeet S. Roychowdhury |
| 1996 | Embedded tutorial: Speed - new paradigms in design for performance. Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy |
| 1996 | Enhancing high-level control-flow for improved testability. Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel |
| 1996 | Expected current distributions for CMOS circuits. Dennis J. Ciplickas, Ronald A. Rohrer |
| 1996 | Exploiting regularity for low-power design. Renu Mehra, Jan M. Rabaey |
| 1996 | Fast Boolean optimization by rewiring. Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska |
| 1996 | GRASP - a new search algorithm for satisfiability. João P. Marques Silva, Karem A. Sakallah |
| 1996 | Generalized constraint generation in the presence of non-deterministic parasitics. Edoardo Charbon, Paolo Miliozzi, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Generation of BDDs from hardware algorithm descriptions. Shin-ichi Minato |
| 1996 | Heterogeneous built-in resiliency of application specific programmable processors. Kyosun Kim, Ramesh Karri, Miodrag Potkonjak |
| 1996 | Hierarchical partitioning. Dirk Behrens, Klaus Harbich, Erich Barke |
| 1996 | Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling. Eric Felt, Stefano Zanella, Carlo Guardiani, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Hybrid floorplanning based on partial clustering and module restructuring. Takayuki Yamanouchi, Kazuo Tamakashi, Takashi Kambe |
| 1996 | Identification of unsettable flip-flops for partial scan and faster ATPG. Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs |
| 1996 | Improved reachability analysis of large finite state machines. Gianpiero Cabodi, Paolo Camurati, Stefano Quer |
| 1996 | Inaccuracies in power estimation during logic synthesis. Daniel Brand, Chandramouli Visweswariah |
| 1996 | Integrated fault diagnosis targeting reduced simulation. Vamsi Boppana, W. Kent Fuchs |
| 1996 | Interchangeable pin routing with application to package layout. Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai |
| 1996 | Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. Hans T. Heineken, Wojciech Maly |
| 1996 | Intranets and EDA: impact, application, and technology. David C. Ku, James A. Rowson |
| 1996 | Jitter-tolerant clock routing in two-phase synchronous systems. Joe G. Xi, Wayne Wei-Ming Dai |
| 1996 | Latch optimization in circuits generated from high-level descriptions. Ellen Sentovich, Horia Toma, Gérard Berry |
| 1996 | Logic optimization by output phase assignment in dynamic logic synthesis. Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser |
| 1996 | Metamorphosis: state assignment by retiming and re-encoding. Balakrishnan Iyer, Maciej J. Ciesielski |
| 1996 | Metrics, techniques and recent developments in mixed-signal testing. Gordon W. Roberts |
| 1996 | Metrology for analog module testing using analog testability bus. Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting |
| 1996 | Minimum replication min-cut partitioning. Wai-Kei Mak, D. F. Wong |
| 1996 | Module placement on BSG-structure and IC layout applications. Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani |
| 1996 | Multi-level logic optimization for low power using local logic transformations. Qi Wang, Sarma B. K. Vrudhula |
| 1996 | Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan |
| 1996 | Noise in deep submicron digital design. Kenneth L. Shepard, Vinod Narayanan |
| 1996 | Optimal non-uniform wire-sizing under the Elmore delay model. Chung-Ping Chen, Hai Zhou, D. F. Wong |
| 1996 | Optimization of custom MOS circuits by transistor sizing. Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah |
| 1996 | Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli |
| 1996 | Polarized observability don't cares. Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk |
| 1996 | Post global routing crosstalk risk estimation and reduction. Tianxiong Xue, Ernest S. Kuh, Dongsheng Wang |
| 1996 | Power optimization in disk-based real-time application specific systems. Inki Hong, Miodrag Potkonjak |
| 1996 | Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996 Rob A. Rutenbar, Ralph H. J. M. Otten |
| 1996 | Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm. Roland W. Freund, Peter Feldmann |
| 1996 | Register-transfer level estimation techniques for switching activity and power consumption. Anand Raghunathan, Sujit Dey, Niraj K. Jha |
| 1996 | SIGMA: a simulator for segment delay faults. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
| 1996 | Semi-analytical techniques for substrate characterization in the design of mixed-signal ICs. Edoardo Charbon, Ranjit Gharpurey, Alberto L. Sangiovanni-Vincentelli, Robert G. Meyer |
| 1996 | Sensitivity analysis of iterative design processes. Eric W. Johnson, Jay B. Brockman |
| 1996 | Sequential redundancy identification using recursive learning. Wanlin Cao, Dhiraj K. Pradhan |
| 1996 | Simulation and sensitivity analysis of transmission line circuits by the characteristics method. Jun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh |
| 1996 | Simulation-based techniques for dynamic test sequence compaction. Elizabeth M. Rudnick, Janak H. Patel |
| 1996 | Software synthesis through task decomposition by dependency analysis. Youngsoo Shin, Kiyoung Choi |
| 1996 | Static timing analysis for self resetting circuits. Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer |
| 1996 | Statistical sampling and regression analysis for RT-level power evaluation. Cheng-Ta Hsieh, Qing Wu, Chih-Shun Ding, Massoud Pedram |
| 1996 | Stratified random sampling for power estimation. Chih-Shun Ding, Cheng-Ta Hsieh, Qing Wu, Massoud Pedram |
| 1996 | Synthesis of reusable DSP cores based on multiple behaviors. Wei Zhao, Christos A. Papachristou |
| 1996 | Synthesis using sequential functional modules (SFMs). Samit Chaudhuri, Michael Quayle |
| 1996 | Tearing based automatic abstraction for CTL model checking. Woohyuk Lee, Abelardo Pardo, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi |
| 1996 | The case for retiming with explicit reset circuitry. Vigyan Singhal, Sharad Malik, Robert K. Brayton |
| 1996 | Timing verification of sequential domino circuits. David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah |
| 1996 | Unit delay simulation with the inversion algorithm. William J. Schilp, Peter M. Maurer |
| 1996 | Using complete-1-distinguishability for FSM equivalence checking. Pranav Ashar, Aarti Gupta, Sharad Malik |
| 1996 | VERILAT: verification using logic augmentation and transformations. Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee |
| 1996 | VLSI circuit partitioning by cluster-removal using iterative improvement techniques. Shantanu Dutt, Wenyong Deng |
| 1996 | Validation coverage analysis for complex digital designs. Richard C. Ho, Mark Horowitz |
| 1996 | Width minimization of two-dimensional CMOS cells using integer programming. Avaneendra Gupta, John P. Hayes |
| 1996 | Zamlog: a parallel algorithm for fault simulation based on Zambezi. Minesh B. Amin, Bapiraju Vinnakota |