| 1995 | A controller-based design-for-testability technique for controller-data path circuits. Sujit Dey, Vijay Gangaram, Miodrag Potkonjak |
| 1995 | A delay model for logic synthesis of continuously-sized networks. Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinori Watanabe |
| 1995 | A fast wavelet collocation method for high-speed VLSI circuit simulation. D. Zhou, N. Chen, W. Cai |
| 1995 | A formal approach to nonlinear analog circuit verification. Lars Hedrich, Erich Barke |
| 1995 | A gradient method on the initial partition of Fiduccia-Mattheyses algorithm. Lung-Tien Liu, Ming-Ter Kuo, Shih-Chen Huang, Chung-Kuan Cheng |
| 1995 | A high-level design and optimization tool for analog RF receiver front-ends. Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen |
| 1995 | A multiple-dominance switch-level model for simulation of short faults. Peter Dahlgren |
| 1995 | A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters. S. R. Kadivar, Doris Schmitt-Landsiedel, Heinrich Klar |
| 1995 | A novel methodology for statistical parameter extraction. Kannan Krishna, Stephen W. Director |
| 1995 | A sequential quadratic programming approach to concurrent gate and wire sizing. Noel Menezes, Ross Baldick, Lawrence T. Pileggi |
| 1995 | A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization. Manfred Henftling, Hannes C. Wittmann, Kurt Antreich |
| 1995 | A timing-driven data path layout synthesis with integer programming. Jaewon Kim, Sung-Mo Kang |
| 1995 | A unified approach to topology generation and area optimization of general floorplans. Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
| 1995 | APPlaUSE: Area and performance optimization in a unified placement and synthesis environment. Elof Frank, Thomas Lengauer |
| 1995 | Acceleration techniques for dynamic vector compaction. Anand Raghunathan, Srimat T. Chakradhar |
| 1995 | Activity-driven clock design for low power circuits. Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh |
| 1995 | Address generation for memories containing multiple arrays. Herman Schmit, Donald E. Thomas |
| 1995 | Addressing high frequency effects in VLSI interconnects with full wave model and CFH. Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang |
| 1995 | An empirical model for accurate estimation of routing delay in FPGAs. Tanay Karnik, Sung-Mo Kang |
| 1995 | An iterative gate sizing approach with accurate delay evaluation. Guangqiu Chen, Hidetoshi Onodera, Keikichi Tamaru |
| 1995 | An iterative improvement algorithm for low power data path synthesis. Anand Raghunathan, Niraj K. Jha |
| 1995 | An optimal algorithm for area minimization of slicing floorplans. Weiping Shi |
| 1995 | Architectural partitioning of control memory for application specific programmable processors. Wei Zhao, Christos A. Papachristou |
| 1995 | Background memory management for dynamic data structure intensive processing systems. Gjalt G. de Jong, Bill Lin, Carl Verdonck, Sven Wuytack, Francky Catthoor |
| 1995 | Be careful with don't cares. Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok |
| 1995 | Binary decision diagrams and beyond: enabling technologies for formal verification. Randal E. Bryant |
| 1995 | Board-level multi-terminal net routing for FPGA-based logic emulation. Wai-Kei Mak, D. F. Wong |
| 1995 | Boolean techniques for low power driven re-synthesis. R. Iris Bahar, Fabio Somenzi |
| 1995 | Bounded-skew clock and Steiner routing under Elmore delay. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao |
| 1995 | CAD challenges in multimedia computing. Paul E. R. Lippens, Vijay Nagasamy, Wayne H. Wolf |
| 1995 | Circuit partitioning with logic perturbation. David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska |
| 1995 | Clock distribution design and verification for PowerPC microprocessors. Shantanu Ganguly, Shervin Hojat |
| 1995 | Communication synthesis for distributed embedded systems. Ti-Yen Yen, Wayne H. Wolf |
| 1995 | Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen |
| 1995 | Constrained multivariable optimization of transmission lines with general topologies. Rohini Gupta, Lawrence T. Pileggi |
| 1995 | Coping with RC(L) interconnect design headaches. Lawrence T. Pileggi |
| 1995 | Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques. Miodrag Potkonjak, Wayne H. Wolf |
| 1995 | Cost-free scan: a low-overhead scan path design methodology. Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen |
| 1995 | Delay optimal partitioning targeting low power VLSI circuits. Hirendu Vaishnav, Massoud Pedram |
| 1995 | Design based analog testing by Characteristic Observation Inference. Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich |
| 1995 | Design verification via simulation and automatic test pattern generation. Hussain Al-Asaad, John P. Hayes |
| 1995 | Design-for-debugging of application specific designs. Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi |
| 1995 | Diagnosis of realistic bridging faults with single stuck-at information. Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee |
| 1995 | Dynamic test signal design for analog ICs. Giri Devarayanadurg, Mani Soma |
| 1995 | Efficient and accurate transient simulation in charge-voltage plane. Anirudh Devgan |
| 1995 | Efficient construction of binary moment diagrams for verifying arithmetic circuits. Kiyoharu Hamaguchi, Akihito Morita, Shuzo Yajima |
| 1995 | Efficient orthonormality testing for synthesis with pass-transistor selectors. Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken |
| 1995 | Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect. Mike Chou, Jacob K. White |
| 1995 | Efficient use of large don't cares in high-level and logic synthesis. Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash |
| 1995 | Efficient validity checking for processor verification. Robert B. Jones, David L. Dill, Jerry R. Burch |
| 1995 | Estimation and bounding of energy consumption in burst-mode control circuits. Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh |
| 1995 | Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits. Chin-Chi Teng, Anthony M. Hill, Sung-Mo Kang |
| 1995 | Extracting RTL models from transistor netlists. K. J. Singh, P. A. Subrahmanyam |
| 1995 | Extraction of circuit models for substrate cross-talk. T. Smedes, N. P. van der Meijs, Arjan J. van Genderen |
| 1995 | Fast discrete function evaluation using decision diagrams. Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia |
| 1995 | Fast functional simulation using branching programs. Pranav Ashar, Sharad Malik |
| 1995 | Fault emulation: a new approach to fault grading. Kwang-Ting Cheng, Shi-Yu Huang, Wei-Jin Dai |
| 1995 | Functional test generation for delay faults in combinational circuits. Irith Pomeranz, Sudhakar M. Reddy |
| 1995 | Gate-level simulation of digital circuits using multi-valued Boolean algebras. Scott Woods, Giorgio Casinovi |
| 1995 | Generating sparse partial inductance matrices with guaranteed stability. Byron Krauter, Lawrence T. Pileggi |
| 1995 | Hierarchical timing analysis using conditional delays. Hakan Yalcin, John P. Hayes |
| 1995 | High-density reachability analysis. Kavita Ravi, Fabio Somenzi |
| 1995 | Hybrid decision diagrams. Edmund M. Clarke, Masahiro Fujita, Xudong Zhao |
| 1995 | Impulse response fault model and fault extraction for functional level analog circuit diagnosis. Chauchin Su, Shenshung Chiang, Shyh-Jye Jou |
| 1995 | Instruction selection using binate covering for code size optimization. Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang |
| 1995 | Interface co-synthesis techniques for embedded systems. Pai H. Chou, Ross B. Ortega, Gaetano Borriello |
| 1995 | LOT: logic optimization with testability-new transformations using recursive learning. Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz |
| 1995 | Linear decomposition algorithm for VLSI design applications. Jianmin Li, John Lillis, Chung-Kuan Cheng |
| 1995 | Logic decomposition during technology mapping. Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness |
| 1995 | Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. Hiroshi Sawada, Takayuki Suyama, Akira Nagoya |
| 1995 | Memory bank and register allocation in software synthesis for ASIPs. Ashok Sudarsanam, Sharad Malik |
| 1995 | Multi-level logic optimization of FSM networks. Huey-Yih Wang, Robert K. Brayton |
| 1995 | New algorithms for min-cut replication in partitioned circuits. Hannah Honghua Yang, D. F. Wong |
| 1995 | On adaptive diagnostic test generation. Yiming Gong, Sreejit Chakravarty |
| 1995 | On testable multipliers for fixed-width data path architectures. Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 1995 | Optimal wire sizing and buffer insertion for low power and a generalized delay model. John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin |
| 1995 | Optimal wiresizing for interconnects with multiple sources. Jason Cong, Lei He |
| 1995 | PARAS: system-level concurrent partitioning and scheduling. Wing Hang Wong, Rajiv Jain |
| 1995 | PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. Roman Kuznar, Franc Brglez |
| 1995 | Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels. Haifang Liao, Wayne Wei-Ming Dai |
| 1995 | Pattern generation for a deterministic BIST scheme. Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich |
| 1995 | Performance estimation of embedded software with instruction cache modeling. Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe |
| 1995 | Performance-driven simultaneous place and route for island-style FPGAs. Sudip K. Nag, Rob A. Rutenbar |
| 1995 | Phantom redundancy: a high-level synthesis approach for manufacturability. Balakrishnan Iyer, Ramesh Karri, Israel Koren |
| 1995 | Post routing performance optimization via multi-link insertion and non-uniform wiresizing. Tianxiong Xue, Ernest S. Kuh |
| 1995 | Power estimation techniques for integrated circuits. Farid N. Najm |
| 1995 | Power vs. delay in gate sizing: conflicting objectives? Sachin S. Sapatnekar, Weitong Chuang |
| 1995 | Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995 Richard L. Rudell |
| 1995 | Pseudo-random testing and signature analysis for mixed-signal circuits. Chen-Yang Pan, Kwang-Ting Cheng |
| 1995 | Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications. Nelson L. Passos, Edwin Hsing-Mean Sha |
| 1995 | Re-engineering of timing constrained placements for regular architectures. Anmol Mathur, Kuang-Chien Chen, C. L. Liu |
| 1995 | Rectangle-packing-based module placement. Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani |
| 1995 | Relaxation-based harmonic balance technique for semiconductor device simulation. Boris Troyanovsky, Zhiping Yu, Lydia So, Robert W. Dutton |
| 1995 | SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits. Nishath K. Verghese, David J. Allstot |
| 1995 | Sequential synthesis using S1S. Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1995 | Signal integrity optimization on the pad assignment for high-speed VLSI design. Kai-Yuan Chao, D. F. Wong |
| 1995 | Single-layer fanout routing and routability analysis for Ball Grid Arrays. Man-Fai Yu, Wayne Wei-Ming Dai |
| 1995 | Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn |
| 1995 | Stable and efficient reduction of substrate model networks using congruence transforms. Kevin J. Kerns, Ivan L. Wemple, Andrew T. Yang |
| 1995 | Statistical behavioral modeling and characterization of A/D converters. Eduardo J. Peralías, Adoración Rueda, José Luis Huertas |
| 1995 | Statistical estimation of sequential circuit activity. Tan-Li Chou, Kaushik Roy |
| 1995 | Switching activity analysis using Boolean approximation method. Taku Uchino, Fumihiro Minami, Takashi Mitsuhashi, Nobuyuki Goto |
| 1995 | Symbolic hazard-free minimization and encoding of asynchronous finite state machines. Robert M. Fuhrer, Bill Lin, Steven M. Nowick |
| 1995 | Synthesis of multiplier-less FIR filters with minimum number of additions. Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1995 | Synthesizing Petri nets from state-based models. Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev |
| 1995 | System partitioning to maximize sleep time. Amir H. Farrahi, Majid Sarrafzadeh |
| 1995 | Technology mapping for field-programmable gate arrays using integer programming. Amit Chowdhary, John P. Hayes |
| 1995 | Test register insertion with minimum hardware cost. Albrecht P. Stroele, Hans-Joachim Wunderlich |
| 1995 | The formal verification of a pipelined double-precision IEEE floating-point multiplier. Mark D. Aagaard, Carl-Johan H. Seger |
| 1995 | Time-Constrained Loop Pipelining. Fermín Sánchez |
| 1995 | Timing analysis with known false sub graphs. Krishna P. Belkhale, Alexander J. Suess |
| 1995 | Two-level logic minimization for low power. Sasan Iman, Massoud Pedram |
| 1995 | Who are the variables in your neighborhood. Shipra Panda, Fabio Somenzi |