ICCAD A

123 papers

YearTitle / Authors
1994A cell-based power estimation in CMOS combinational circuits.
Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen
1994A comprehensive fault macromodel for opamps.
Chen-Yang Pan, Kwang-Ting Cheng, Sandeep Gupta
1994A fast and memory-efficient diagnostic fault simulation for sequential circuits.
Jer-Min Jou, Shung-Chih Chen
1994A formal basis for design process planning and management.
Margarida F. Jacome, Stephen W. Director
1994A general framework for vertex orderings, with applications to netlist clustering.
Charles J. Alpert, Andrew B. Kahng
1994A loosely coupled parallel algorithm for standard cell placement.
Wern-Jieh Sun, Carl Sechen
1994A new approach for factorizing FSM's.
Chunduri Rama Mohan, Partha Pratim Chakrabarti
1994A new built-in self-test approach for digital-to-analog and analog-to-digital converters.
Karim Arabi, Bozena Kaminska, Janusz Rzeszut
1994A new efficient approach to statistical delay modeling of CMOS digital combinational circuits.
Syed A. Aftab, M. A. Styblinski
1994A new global routing algorithm for FPGAs.
Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong
1994A precorrected-FFT method for capacitance extraction of complicated 3-D structures.
Joel R. Phillips, Jacob K. White
1994A redesign technique for combinational circuits based on gate reconnections.
Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton
1994A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays.
Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki
1994A specified delay accomplishing clock router using multiple layers.
Mitsuho Seki, Kenji Inoue, Kazuo Kato, Kouki Tsurusaki, Shin'ichi Fukasawa, Hitoshi Sasaki, Mutsuhito Aizawa
1994A statistical optimization-based approach for automated sizing of analog cells.
Fernando Medeiro, Francisco V. Fernández, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez
1994A symbolic method to reduce power consumption of circuits containing false paths.
R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
1994A timing analysis algorithm for circuits with level-sensitive latches.
Jin-Fuw Lee, Donald T. Tang, C. K. Wong
1994Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis.
Jörg Henkel, Rolf Ernst, Ulrich Holtmann, Thomas Benner
1994Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays.
Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato
1994Algorithm selection: a quantitative computation-intensive optimization approach.
Miodrag Potkonjak, Jan M. Rabaey
1994An efficient procedure for the synthesis of fast self-testable controller structures.
Sybille Hellebrand, Hans-Joachim Wunderlich
1994An enhanced flow model for constraint handling in hierarchical multi-view design environments.
Pieter van der Wolf, K. Olav ten Bosch, Alfred van der Hoeven
1994An object-oriented cell library manager.
Naresh Sehgal, C. Y. Roger Chen, John M. Acken
1994Analytical fault modeling and static test generation for analog ICs.
Giri Devarayanadurg, Mani Soma
1994Approximate symbolic analysis of large analog integrated circuits.
Qicheng Yu, Carl Sechen
1994Area minimization for hierarchical floorplans.
Peichen Pan, Weiping Shi, C. L. Liu
1994Automatic test program generation for pipelined processors.
Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose
1994Boolean constrained encoding: a new formulation and a case study.
Ney Laert Vilar Calazans
1994Built-in self-test and fault diagnosis of fully differential analogue circuits.
Salvador Mir, Vladimir Kolarik, Marcelo Lubaszewski, C. Nielsen, Bernard Courtois
1994Capturing time-of-flight delay for transient analysis based on scattering parameter macromodel.
Haifang Liao, Wayne Wei-Ming Dai
1994Channel-driven global routing with consistent placement (extended abstract).
Shigetoshi Nakatake, Yoji Kajitani
1994Clock period constrained minimal buffer insertion in clock trees.
Gustavo E. Téllez, Majid Sarrafzadeh
1994Comprehensive lower bound estimation from behavioral descriptions.
Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt
1994Compression-relaxation: a new approach to performance driven placement for regular architectures.
Anmol Mathur, C. L. Liu
1994Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator.
Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
1994Condition graphs for high-quality behavioral synthesis.
Hsiao-Ping Juan, Viraphol Chaiyakul, Daniel D. Gajski
1994Dataflow-driven memory allocation for multi-dimensional signal processing systems.
Florin Balasa, Francky Catthoor, Hugo De Man
1994Decomposition methods for library binding of speed-independent asynchronous designs.
Polly Siegel, Giovanni De Micheli
1994Definition and solution of the memory packing problem for field-programmable systems.
David Karchmer, Jonathan Rose
1994Delay and area optimization for compact placement by gate resizing and relocation.
Weitong Chuang, Ibrahim N. Hajj
1994Design exploration for high-performance pipelines.
Smita Bakshi, Daniel D. Gajski
1994Design of heterogeneous ICs for mobile and personal communication systems.
Gert Goossens, Ivo Bolsens, Bill Lin, Francky Catthoor
1994Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints.
Claudionor José Nunes Coelho Jr., Giovanni De Micheli
1994Dynamical identification of critical paths for iterative gate sizing.
How-Rern Lin, TingTing Hwang
1994Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs.
Hannah Honghua Yang, D. F. Wong
1994Efficient breadth-first manipulation of binary decision diagrams.
Pranav Ashar, Matthew Cheong
1994Efficient implementation of retiming.
Narendra V. Shenoy, Richard L. Rudell
1994Efficient network flow based min-cut balanced partitioning.
Honghua Yang, D. F. Wong
1994Efficient small-signal circuit analysis and sensitivity computations with the PVL algorithm.
Roland W. Freund, Peter Feldmann
1994Embedded systems design for low energy consumption.
Michael A. Schuette, John R. Barr
1994Estimation of circuit activity considering signal correlations and simultaneous switching.
Tan-Li Chou, Kaushik Roy, Sharat Prasad
1994Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics.
Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee
1994Fast timing simulation of transient faults in digital circuits.
Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel
1994Fast transient power and noise estimation for VLSI circuits.
Wolfgang T. Eisenmann, Helmut E. Graeb
1994Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring.
Georges G. E. Gielen, Zhihua Wang, Willy M. C. Sansen
1994Fault dictionary compaction by output sequence removal.
Vamsi Boppana, W. Kent Fuchs
1994Folding a stack of equal width components.
Venkat Thanvantri, Sartaj K. Sahni
1994Generating instruction sets and microarchitectures from applications.
Ing-Jer Huang, Alvin M. Despain
1994HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults.
Chen-Pin Kung, Chen-Shang Lin
1994Improving over-the-cell channel routing in standard cell design.
Xiaolin Liu, Ioannis G. Tollis
1994Incremental formal design verification.
Gitanjali Swamy, Robert K. Brayton
1994Incremental synthesis.
Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain
1994Integrating program transformations in the memory-based synthesis of image and video algorithms.
David J. Kolson, Alexandru Nicolau, Nikil D. Dutt
1994Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0.
Daniel G. Saab, Youssef Saab, Jacob A. Abraham
1994Iterative algorithms for formal verification of embedded real-time systems.
Felice Balarin, Alberto L. Sangiovanni-Vincentelli
1994LP based cell selection with constraints of timing, area, and power consumption.
Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita
1994Layer assignment for high-performance multi-chip modules.
Kai-Yuan Chao, D. F. Wong
1994Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection.
Nur A. Touba, Edward J. McCluskey
1994Low power state assignment targeting two-and multi-level logic implementations.
Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain
1994Low-cost single-layer clock trees with exact zero Elmore delay skew.
Andrew B. Kahng, Chung-Wen Albert Tsao
1994Macromodeling of analog circuits for hierarchical circuit design.
Jianfeng Shao, Ramesh Harjani
1994Measurement and modeling of MOS transistor current mismatch in analog IC's.
Eric Felt, Amit Narayan, Alberto L. Sangiovanni-Vincentelli
1994Minimum crosstalk switchbox routing.
Tong Gao, C. L. Liu
1994Module selection and data format conversion for cost-optimal DSP synthesis.
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
1994Multi-level logic optimization by implication analysis.
Wolfgang Kunz, Prem R. Menon
1994Multi-level network optimization for low power.
Sasan Iman, Massoud Pedram
1994Multi-level synthesis for safe replaceability.
Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton
1994Multi-way VLSI circuit partitioning based on dual net representation.
Jason Cong, Wilburt Labio, Narayanan Shivakumar
1994Non-scan design-for-testability of RT-level data paths.
Sujit Dey, Miodrag Potkonjak
1994On error correction in macro-based circuits.
Irith Pomeranz, Sudhakar M. Reddy
1994On modeling top-down VLSI design.
Bernd Schürmann, Joachim Altmeyer, Martin Schütze
1994On testing delay faults in macro-based combinational circuits.
Irith Pomeranz, Sudhakar M. Reddy
1994On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution.
Yu-Liang Wu, Douglas Chang
1994Optimal latch mapping and retiming within a tree.
Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann
1994Optimization of critical paths in circuits with level-sensitive latches.
Timothy M. Burks, Karem A. Sakallah
1994Optimization of hierarchical designs using partitioning and resynthesis.
Heinz-Josef Eikerling, Ralf Hunstock, Raul Camposano
1994Performance-driven synthesis of asynchronous controllers.
Kenneth Y. Yun, Bill Lin, David L. Dill, Srinivas Devadas
1994Perturb and simplify: multi-level boolean network optimizer.
Shih-Chieh Chang, Malgorzata Marek-Sadowska
1994Power analysis of embedded software: a first step towards software power minimization.
Vivek Tiwari, Sharad Malik, Andrew Wolfe
1994Precomputation-based sequential logic optimization for low power.
Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
1994Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994
Jochen A. G. Jess, Richard L. Rudell
1994Process-variation-tolerant clock skew minimization.
Shen Lin, C. K. Wong
1994Provably correct high-level timing analysis without path sensitization.
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
1994RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults.
Abhijit Chatterjee, Jacob A. Abraham
1994RC interconnect synthesis-a moment fitting approach.
Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage
1994RISA: accurate and efficient placement routability modeling.
Chih-Liang Eric Cheng
1994Random pattern testable logic synthesis.
Chen-Huan Chiang, Sandeep K. Gupta
1994Re-encoding sequential circuits to reduce power dissipation.
Gary D. Hachtel, Mariano Hermida de la Rica, Abelardo Pardo, Massimo Poncino, Fabio Somenzi
1994Register assignment through resource classification for ASIP microcode generation.
Clifford Liem, Trevor C. May, Pierre G. Paulin
1994Retiming with non-zero clock skew, variable register, and interconnect delay.
Tolga Soyata, Eby G. Friedman
1994Reuse of design objects in CAD frameworks.
Joachim Altmeyer, Stefan Ohnsorge, Bernd Schürmann
1994Selecting partial scan flip-flops for circuit partitioning.
Toshinobu Ono
1994Simulation of digital circuits in the presence of uncertainty.
Mark H. Linderman, Miriam Leeser
1994Simultaneous driver and wire sizing for performance and power optimization.
Jason Cong, Cheng-Kok Koh
1994Simultaneous functional-unit binding and floorplanning.
Yung-Ming Fang, D. F. Wong
1994Skew sensitivity minimization of buffered clock tree.
Jae Chung, Chung-Kuan Cheng
1994Switching activity analysis considering spatiotemporal correlations.
Radu Marculescu, Diana Marculescu, Massoud Pedram
1994Symmetry detection and dynamic variable ordering of decision diagrams.
Shipra Panda, Fabio Somenzi, Bernard Plessier
1994Synthesis of concurrent system interface modules with automatic protocol conversion generation.
Bill Lin, Steven Vercauteren
1994Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams.
Bill Lin, Srinivas Devadas
1994Synthesis of manufacturable analog circuits.
Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar
1994Techniques for crosstalk avoidance in the physical design of high-performance digital systems.
Desmond Kirkpatrick, Alberto L. Sangiovanni-Vincentelli
1994Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation.
Uwe Gläser, Heinrich Theodor Vierhaus, M. Kley, A. Wiederhold
1994Test pattern generation based on arithmetic operations.
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
1994Testing of analog systems using behavioral models and optimal experimental design techniques.
Eric Felt, Alberto L. Sangiovanni-Vincentelli
1994The Inversion Algorithm for digital simulation.
Peter M. Maurer
1994The reproducing placement problem with applications.
Wei-Liang Lin, Majid Sarrafzadeh, Chak-Kuen Wong
1994Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations.
Alper Demir, Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli
1994Timing uncertainty analysis for time-of-flight systems.
John R. Feehrer, Harry F. Jordan
1994Towards support for design description languages in EDA framework.
Olav Schettler, Susanne Heymann
1994Unified complete MOSFET model for analysis of digital and analog circuits.
Mitiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac
1994Universal logic gate for FPGA design.
Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin
1994VLSI timing simulation with selective dynamic regionization.
Meng-Lin Yu, Bryan D. Ackland