ICCAD A

123 papers

YearTitle / Authors
1993A combined hierarchical placement algorithm.
Hyunchul Shin, Chunghee Kim, Wonjong Kim, Myoungsub Oh, Kwangjoon Rhee, Seogyun Choi, Heasoo Chung
1993A fast algorithm for VLSI net extraction.
Mario Alberto López, Ravi Janardan, Sartaj K. Sahni
1993A flexible statistical model for CAD of submicrometer analog CMOS integrated circuits.
Christopher Michael, Christopher J. Abel, C. S. Teng
1993A flow-based user interface for efficient execution of the design cycle.
K. Olav ten Bosch, Pieter van der Wolf, Peter Bingley
1993A general consistency technique for increasing the controllability of high level synthesis tools.
Lawrence F. Arnstein, Donald E. Thomas
1993A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths.
Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Ting-Chung Chang
1993A grid-based approach for connectivity binding with geometric costs.
Hyuk-Jae Jang, Barry M. Pangrle
1993A net-oriented method for realistic fault analysis.
Hua Xue, Chennian Di, Jochen A. G. Jess
1993A new feed-through assignment algorithm based on a flow model.
Takumi Okamoto, Masaki Ishikawa, Tomoyuki Fujita
1993A new generalized row-based global router.
William Swartz, Carl Sechen
1993A relaxation/multipole-accelerated scheme for self-consistent electromechanical analysis of complex 3-D microelectromechanical structures.
Xuejun Cai, He Yie, Peter Osterberg, John Gilbert, Stephen D. Senturia, Jacob K. White
1993A simple algorithm for fanout optimization using high-performance buffer libraries.
K. Kodandapani, Joel Grodstein, Antun Domic, Hervé J. Touati
1993A spacing algorithm for performance enhancement and cross-talk reduction.
Kamal Chaudhary, Akira Onozawa, Ernest S. Kuh
1993A symbolic algorithm for maximum flow in 0-1 networks.
Gary D. Hachtel, Fabio Somenzi
1993A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area.
Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj
1993A unified approach to simulating electrical and thermal substrate coupling interactions in ICs.
Nishath K. Verghese, Sang-Soo Lee, David J. Allstot
1993A visual design environment.
Eric J. Golin, Annette C. Feng, Linus Huang, Eric Hughes
1993Accelerated waveform methods for parallel transient simulation of semiconductor devices.
Mark W. Reichelt, Andrew Lumsdaine, Jacob K. White
1993Algebraic decision diagrams and their applications.
R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
1993Allocation of multiport memories for hierarchical data stream.
Paul E. R. Lippens, Jef L. van Meerbergen, Wim F. J. Verhaegh, Albert van der Werf
1993An ASIP instruction set optimization algorithm with functional module sharing constraint.
Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi
1993An accurate grid local truncation error for device simulation.
Mi-Chang Chang, Jue-Hsien Chern, Ping Yang
1993An algorithm for improving partitions of pin-limited multi-chip systems.
Mark Beardslee, Alberto L. Sangiovanni-Vincentelli
1993An efficient algorithm for the net matching problem.
Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita
1993An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules.
S. Y. Kim, Emre Tuncer, Rohini Gupta, Byron Krauter, Thomas L. Savarino, Dean P. Neikirk, Lawrence T. Pillage
1993An improved method for RTL synthesis with testability tradeoffs.
Haidar Harmanani, Christos A. Papachristou
1993Analysis of cyclic combinational circuits.
Sharad Malik
1993Architecture and routability analysis for row-based FPGAs.
Massoud Pedram, Bahman S. Nobandegani, Bryan Preas
1993Augmented partial reset.
Ben Mathew, Daniel G. Saab
1993Behavior tables: a basis for system representation and transformational system synthesis.
Kamlesh Rath, M. Esen Tuna, Steven D. Johnson
1993Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.
Jason Cong, Yuzheng Ding
1993Boolean algebraic test generation using a distributed system.
Debashis Bhattacharya, Prathima Agrawal
1993Boolean factorization using multiple-valued minimization.
Stan Y. Liao, Srinivas Devadas, Abhijit Ghosh
1993Boolean matching for full-custom ECL gates.
Robert N. Mayo, Hervé J. Touati
1993Bounds on net lengths for high-speed PCB.
Jaebum Lee, Eugene Shragowitz, David J. Poli
1993Breadth-first manipulation of very large binary-decision diagrams.
Hiroyuki Ochi, Koichi Yasuoka, Shuzo Yajima
1993Buffer assignment for data driven architectures.
Dhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee
1993Cellular automata based synthesis of easily and fully testable FSMs.
Dipanwita Roy Chowdhury, Supratik Chakraborty, B. Vamsi, B. Pal Chaudhuri
1993Combining technology mapping and placement for delay-optimization in FPGA designs.
Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
1993Computing the observable equivalence relation of a finite state machine.
Thomas Tamisier
1993Convexity-based algorithms for design centering.
Sachin S. Sapatnekar, Pravin M. Vaidya, Steve M. Kang
1993Cube-packing and two-level minimization.
Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993Design tool integration using object-oriented database views.
Elke A. Rundensteiner
1993Detection of symmetry of Boolean functions represented by ROBDDs.
Dirk Möller, Janett Mohnke, Michael Weber
1993Dynamic variable ordering for ordered binary decision diagrams.
Richard Rudell
1993Efficient and effective placement for very large circuits.
Wern-Jieh Sun, Carl Sechen
1993Efficient estimation of dynamic power consumption under a real delay model.
Chi-Ying Tsui, Massoud Pedram, Alvin M. Despain
1993Efficient modeling of switch-level networks containing undetermined logic node states.
Peter Dahlgren, Peter Lidén
1993Efficient verification of determinate speed-independent circuits.
Peter A. Beerel, Jerry R. Burch, Teresa H.-Y. Meng
1993Event driven adaptively controlled explicit simulation of integrated circuits.
Anirudh Devgan, Ronald A. Rohrer
1993Exact evaluation of memory size for multi-dimensional signal processing systems.
Florin Balasa, Francky Catthoor, Hugo De Man
1993Execution interval analysis under resource constraints.
Adwin H. Timmer, Jochen A. G. Jess
1993Exploiting hardware sharing in high-level synthesis for partial scan optimization.
Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy
1993FGILP: an integer linear program solver based on function graphs.
Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula
1993Fault behavior dictionary for simulation of device-level transients.
Gwan S. Choi, Ravishankar K. Iyer, Daniel G. Saab
1993Fault dictionary compression and equivalence class computation for sequential circuits.
Paul G. Ryan, W. Kent Fuchs, Irith Pomeranz
1993Fault-based automatic test generator for linear analog circuits.
Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham
1993Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits.
Kerry S. Lowe, P. Glenn Gulak
1993Generalized constraint generation for analog circuit design.
Edoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli
1993HANNIBAL: an efficient tool for logic verification based on recursive learning.
Wolfgang Kunz
1993Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors.
Ing-Jer Huang, Alvin M. Despain
1993Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures.
Arjan J. van Genderen, N. P. van der Meijs
1993High level synthesis for reconfigurable datapath structures.
Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
1993High throughput pipelined data path synthesis by conserving the regularity of nested loops.
Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee
1993Input don't care sequences in FSM networks.
Huey-Yih Wang, Robert K. Brayton
1993Instruction set mapping for performance optimization.
Miguel R. Corazao, Marwan A. Khalaf, Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey
1993Interleaving based variable ordering methods for ordered binary decision diagrams.
Hiroshige Fujii, Goichi Ootomo, Chikahiro Hori
1993Inverter minimization in multi-level logic networks.
Alok Jain, Randal E. Bryant
1993Latchup-aware placement and parasitic-bounded routing of custom analog cells.
Bülent Basaran, Rob A. Rutenbar, L. Richard Carley
1993Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's.
Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru
1993Logic partitioning to pseudo-exhaustive test for BIST design.
Chien-In Henry Chen, Joel T. Yuen
1993Macromodeling of the A.C. characteristics of CMOS Op-amps.
Pradip Mandal, V. Visvanathan
1993Maximum projections of don't care conditions in a Boolean network.
Ted Stanion, Carl Sechen
1993Merging multiple FSM controllers for DFT/BIST hardware.
Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer
1993Min-max linear programming and the timing analysis of digital circuits.
Timothy M. Burks, Karem A. Sakallah
1993Minimum crosstalk channel routing.
Tong Gao, C. L. Liu
1993Minimum padding to satisfy short path constraints.
Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993Modeling hierarchical combinational circuits.
Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli
1993New faster Kernighan-Lin-type graph-partitioning algorithms.
Shantanu Dutt
1993New methods for parallel pattern fast fault simulation for synchronous sequential circuits.
Mehrdad Mojtahedi, Walter Geisselhardt
1993New methods of improving parallel fault simulation in synchronous sequential circuits.
Hyung Ki Lee, Dong Sam Ha
1993Nyquist data converter testing and yield analysis using behavioral simulation.
Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli
1993On diagnosis and correction of design errors.
Irith Pomeranz, Sudhakar M. Reddy
1993On-chip test generation for combinational circuits by LFSR modification.
Shambhu J. Upadhyaya, Liang-Chi Chen
1993Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models.
Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi
1993Optimal wiresizing under the distributed Elmore delay model.
Jason Cong, Kwok-Shing Leung
1993Parallel multi-delay simulation.
Yun Sik Lee, Peter M. Maurer
1993Parallel timing simulation on a distributed memory multiprocessor.
Chih-Po Wen, Katherine A. Yelick
1993Partitioning with cone structures.
Gabriele Saucier, Daniel R. Brasen, J. P. Hiol
1993Performance-driven partitioning using retiming and replication.
Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku
1993Piecewise linear models for Rsim.
Russell Kao, Mark Horowitz
1993Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs.
Enric Pastor, Jordi Cortadella
1993Practical applications of an efficient time separation of events algorithm.
Henrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello
1993Probabilistic construction and manipulation of free Boolean diagrams.
Amelia Shen, Srinivas Devadas, Abhijit Ghosh
1993Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993
Michael R. Lightner, Jochen A. G. Jess
1993Quadratic zero-one programming based synthesis of application specific data paths.
Werner Geurts, Francky Catthoor, Hugo De Man
1993Rapid prototyping of microprocessor-based systems.
Raj S. Mitra, Biswaroop Guha, Anupam Basu
1993Reconfigurable scan chains: a novel approach to reduce test application time.
Sridhar Narayanan, Melvin A. Breuer
1993Representation and symbolic manipulation of linearly inductive Boolean functions.
Aarti Gupta, Allan L. Fisher
1993Retiming gated-clocks and precharged circuit structures.
Alexander T. Ishii
1993Retiming sequential circuits for low power.
José Monteiro, Srinivas Devadas, Abhijit Ghosh
1993Routing for symmetric FPGAs and FPICs.
Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu
1993Run-time requirement tracing.
Andrea Casotto
1993SEFOP: a novel approach to data path module placement.
Chih-Liang Eric Cheng, Ching-Yen Ho
1993Scheduling a minimum dependence in FSMs.
Steve C.-Y. Huang, Wayne H. Wolf
1993Sequential logic optimization by redundancy addition and removal.
Luis Entrena, Kwang-Ting Cheng
1993Simulating 3-D retarded interconnect models using complex frequency hopping (CFH).
Eli Chiprout, Hansruedi Heeb, Michel S. Nakhla, Albert E. Ruehli
1993Simulating sigma-delta modulators in AWEswit.
Richard J. Trihy, Ronald A. Rohrer
1993Sizing and verification of communication buffers for communicating processes.
Tilman Kolks, Bill Lin, Hugo De Man
1993State look ahead technique for cycle optimization of interacting finite state Moore machines.
Wolfgang Ecker, Michael Hofmeister
1993Style: a technology-independent approach to statistical design.
Julie Chen, Andrew T. Yang
1993Switch module design with application to two-dimensional segmentation design.
Kai Zhu, D. F. Wong, Yao-Wen Chang
1993Test generation for multiple faults based on parallel vector pair analysis.
Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita
1993Test generation for path delay faults based on learning.
Irith Pomeranz, Sudhakar M. Reddy
1993Test quality and yield analysis using the DEFAM defect to fault mapper.
Dinesh D. Gaitonde, Duncan M. Hank Walker
1993The maximum set of permissible behaviors for FSM networks.
Yosinori Watanabe, Robert K. Brayton
1993The practical application of retiming to the design of high-performance systems.
Brian Lockyear, Carl Ebeling
1993Transforming an arbitrary floorplan into a sliceable one.
Majid Sarrafzadeh
1993Tree-based mapping of algorithms to predefined structures.
Peter Marwedel
1993Tri-state bus conflict checking method for ATPG using BDD.
Yasushi Koseko, Takuji Ogihara, Shinichi Murai
1993Unifying synchronous/asynchronous state machine synthesis.
Kenneth Y. Yun, David L. Dill
1993Unifying test and diagnosis of interconnects and logic clusters in partial boundary scan boards.
Meryem Marzouki, Marcelo Lubaszewski, Mohamed Hedi Touati
1993Verification of large synthesized designs.
Daniel Brand