| 1992 | 1992 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of Technical Papers Louise Trevillyan, Michael R. Lightner |
| 1992 | A comparative study of design for testability methods using high-level and gate-level descriptions. Vivek Chickermane, Jaushin Lee, Janak H. Patel |
| 1992 | A generalized state assignment theory for transformation on signal transition graphs. Peter Vanbekbergen, Bill Lin, Gert Goossens, Hugo De Man |
| 1992 | A logic simulation engine based on a modified data flow architecture. Ausif Mahmood, William I. Baker, Jayantha A. Herath, Anura P. Jayasumana |
| 1992 | A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling. Kimon W. Michaels, Andrzej J. Strojwas |
| 1992 | A new algorithm for the binate covering problem and its application to the minimization of Boolean relations. Seh-Woong Jeong, Fabio Somenzi |
| 1992 | A new approach to effective circuit clustering. Lars W. Hagen, Andrew B. Kahng |
| 1992 | A partitioning algorithm for system-level synthesis. G. Menez, Michel Auguin, Fernand Boéri, C. Carrière |
| 1992 | A probabilistic multicommodity-flow solution to circuit clustering problems. Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin |
| 1992 | A probabilistic timing approach to hot-carrier effect estimation. Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj |
| 1992 | A scheduling method by stepwise expansion in high-level synthesis. Hironori Komi, Shoichiro Yamada, Kunio Fukunaga |
| 1992 | A tutorial on logic synthesis for lookup-table based FPGAs. Robert J. Francis |
| 1992 | A unified signal transition graph model for asynchronous control circuit synthesis. Alexandre Yakovlev, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
| 1992 | A wire-length minimization algorithm for single-layer layouts. De-Sheng Chen, Majid Sarrafzadeh |
| 1992 | A zero-skew clock routing scheme for VLSI circuits. Ying-Meng Li, Marwan A. Jabri |
| 1992 | AWE macromodels of VLSI interconnect for circuit simulation. Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage |
| 1992 | Accuate simplification of large symbolic formulae. Francisco V. Fernández, Ángel Rodríguez-Vázquez, J. D. Martín, José L. Huertas |
| 1992 | Accurate layout area and delay modeling for system level design. Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul |
| 1992 | Accurate net models for placement improvement by network flow methods. Konrad Doll, Frank M. Johannes, Georg Sigl |
| 1992 | Aesthetic routing for transistor schematics. Tsung D. Lee, Lawrence P. McNamee |
| 1992 | An algorithm to reduce test application time in full scan designs. Soo Young Lee, Kewal K. Saluja |
| 1992 | An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines. Ali El-Zein, Salim Chowdhury |
| 1992 | An effective methodology for functional pipelining. Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin |
| 1992 | An efficient multi-view design model for real-time interactive synthesis. Allen C.-H. Wu, Tedd Hadley, Daniel Gajski |
| 1992 | An efficient non-enumerative method to estimate path delay fault coverage. Irith Pomeranz, Sudhakar M. Reddy |
| 1992 | An optimal chip compaction method based on shortest path algorithm with automatic jog insertion. Toru Awashima, Wataru Yamamoto, Masao Sato, Tatsuo Ohtsuki |
| 1992 | An optimal probe testing algorithm for the connectivity verification of MCM substrates. So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu |
| 1992 | An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. Jason Cong, Yuzheng Ding |
| 1992 | Analytic macromodeling and simulation fo tightly-coupled mixed analog-digital circuits. Yu-Hsu Chang, Andrew T. Yang |
| 1992 | Area minimization for general floorplans. Peichen Pan, C. L. Liu |
| 1992 | Area optimization of multi-functional processing units. Albert van der Werf, M. J. H. Peek, Emile H. L. Aarts, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh |
| 1992 | Assignment of global memory elements for multi-process VHDL specifications. Heinrich Krämer, Jens Müller |
| 1992 | Automatic compositional minimization in CTL model checking. Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton |
| 1992 | Automatic differentiation in circuit simulation and device modeling. Peter Feldmann, Robert C. Melville, Shahriar Moinian |
| 1992 | Automatic gate-level synthesis of speed-independent circuits. Peter A. Beerel, Teresa H.-Y. Meng |
| 1992 | Automatic generation and verification of sufficient correctness properties for synchronous processors. Filip Van Aelten, Stan Y. Liao, Jonathan Allen, Srinivas Devadas |
| 1992 | Automatic synthesis of 3D asynchronous state machines. Kenneth Y. Yun, David L. Dill |
| 1992 | Automatic test generation for linear digital systems with bi-level search using matrix transform methods. Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu |
| 1992 | Behavioral simulation for noise in mixed-mode sampled-data systems. Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli |
| 1992 | Behavioral synthesis for easy testability in data path scheduling. Tien-Chien Lee, Wayne H. Wolf, Niraj K. Jha |
| 1992 | Behavioral synthesis for testability. Chung-Hsing Chen, Daniel G. Saab |
| 1992 | COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy |
| 1992 | CRIS: a test cultivation program for sequential VLSI circuits. Daniel G. Saab, Youssef Saab, Jacob A. Abraham |
| 1992 | Cloning techniques for hierarchical compaction. Ravi Varadarajan, Cyrus Bamji |
| 1992 | Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices. Yoon-Hwa Choi, Taechul Jung |
| 1992 | Configuring multiple scan chains for minimum test time. Sridhar Narayanan, Rajesh Gupta, Melvin A. Breuer |
| 1992 | DAMOCLES: an observer-based approach to design tracking. Venu Vasudevan, Yves Mathys, Jim Tolar |
| 1992 | DECOR - tightly integrated Design Control and Observation. Elisabeth Kupitz, Jürgen Tacken |
| 1992 | Delay and bus current evaluation in CMOS logic circuits. Abdolreza Nabavi-Lishi, Nicholas C. Rumin |
| 1992 | Design of system interface modules. Jane S. Sun, Robert W. Brodersen |
| 1992 | Detailed layer assignment for MCM routing. Mysore Sriram, Sung-Mo Kang |
| 1992 | E-PROOFS: a CMOS bridging fault simulator. Gary S. Greenstein, Janak H. Patel |
| 1992 | ETA: electrical-level timing analysis. Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage |
| 1992 | Efficiency improvements for force-directed scheduling. Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jan H. M. Korst, Albert van der Werf, Jef L. van Meerbergen |
| 1992 | Efficient Boolean function matching. Jerry R. Burch, David E. Long |
| 1992 | Efficient partitioning and analysis of digital CMOS-circuits. Uwe Hübner, Heinrich Theodor Vierhaus |
| 1992 | Efficient techniques for inductance extraction of complex 3-D geometries. Mattan Kamon, Michael J. Tsuk, C. Smithhisler, Jacob K. White |
| 1992 | Engineering education: trends and needs (panel). Stephen W. Director, Jonathan Allen, J. Duley |
| 1992 | Equivalent design representations and transformations for interactive scheduling. Roger P. Ang, Nikil D. Dutt |
| 1992 | Exact two-level minimization of hazard-free logic with multiple-input changes. Steven M. Nowick, David L. Dill |
| 1992 | Exhaustive simulation need not require an exponential number of tests. Daniel Brand |
| 1992 | Exploiting multi-cycle false paths in the performance optimization of sequential circuits. Pranav Ashar, Sujit Dey, Sharad Malik |
| 1992 | Extension of the asymptotic waveform evaluation technique with the method of characteristics. J. Eric Bracken, Vivek Raghavan, Ronald A. Rohrer |
| 1992 | FICOM: a framework for incremental consistency maintenance in multi-representation, structural VLSI databases. Robert C. Armstrong, Jonathan Allen |
| 1992 | False loops through resource sharing. Leon Stok |
| 1992 | Graph algorithms for clock schedule optimization. Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | HERO: hierarchical EMC-constrained routing. Dirk Theune, Ralf Thiele, Thomas Lengauer, Anja Feldmann |
| 1992 | HIMALAYAS - a hierarchical compaction system with a minimized constraint set. Jin-Fuw Lee, Donald T. Tang |
| 1992 | HYPER-LP: a system for power minimization using architectural transformations. Anantha P. Chandrakasan, Miodrag Potkonjak, Jan M. Rabaey, Robert W. Brodersen |
| 1992 | Hazard-non-increasing gate-level optimization algorithms. David S. Kung |
| 1992 | Identification of critical paths in circuits with level-sensitive latches. Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge |
| 1992 | Incorporating design flow management in a framework based CAD system. Peter Bingley, K. Olav ten Bosch, Pieter van der Wolf |
| 1992 | Lazy-expansion symbolic expression approximation in SYNAP. Steven J. Seda, Marc G. R. Degrauwe, Wolfgang Fichtner |
| 1992 | MOSAIC: a tile-based datapath layout generator. Goro Suzuki, Tetsuya Yamamoto, Kyoji Yuyama, Kotaro Hirasawa |
| 1992 | Maximally fast and arbitrarily fast implementation of linear computations. Miodrag Potkonjak, Jan M. Rabaey |
| 1992 | Maze router without a grid map. Jiri Soukup |
| 1992 | McPOWER: a Monte Carlo approach to power estimation. Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick |
| 1992 | New channel segmentation model and associated routing algorithm for high performance FPGAs. Surendra Burman, Chandar Kamalanathan, Naveed A. Sherwani |
| 1992 | Numerical integration algorithms and asymptotic waveform evaluation (AWE). M. Murat Alaybeyi, John Y. Lee, Ronald A. Rohrer |
| 1992 | On average power dissipation and random pattern testability of CMOS combinational logic networks. Amelia Shen, Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer |
| 1992 | On channel segmentation design for row-based FPGAs. Kai Zhu, D. F. Wong |
| 1992 | On the generation of small dictionaries for fault location. Irith Pomeranz, Sudhakar M. Reddy |
| 1992 | On the verification of state-coding in STGs. Kuan-Jen Lin, Chen-Shang Lin |
| 1992 | Optimal replication for min-cut partitioning. L. James Hwang, Abbas El Gamal |
| 1992 | Optimal synthesis of multichip architectures. Catherine H. Gebotys |
| 1992 | Overall consideration of scan design and test generation. Pao-Chuan Chen, Bin-Da Liu, Jhing-Fa Wang |
| 1992 | Parallel logic and fault simulation algorithms for shared memory vector machines. Abdulla Bataineh, Füsun Özgüner, Imre Szauter |
| 1992 | Perfect-balance planar clock routing with minimal path-length. Qing Zhu, Wayne Wei-Ming Dai |
| 1992 | Performance optimization of sequential circuits by eliminating retiming bottlenecks. Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler |
| 1992 | Portable parallel test generation for sequential circuits. Balkrishna Ramkumar, Prithviraj Banerjee |
| 1992 | Power estimation tool for sub-micron CMOS VLSI circuits. F. Rouatbi, Baher Haroun, Asim J. Al-Khalili |
| 1992 | Precise timing verification of logic circuits under combined delay model. Shinji Kimura, Shigemi Kashima, Hiromasa Haneda |
| 1992 | ProperSYN: a portable parallel algorithm for logic synthesis. Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee |
| 1992 | Ravel: assigned-delay compiled-code logic simulation. Emily J. Shriver, Karem A. Sakallah |
| 1992 | Reconfigurable machine and its application to logic diagnosis. Naoaki Suganuma, Yukihiro Murata, Satoru Nakata, Shinichi Nagata, Masahiro Tomita, Kotaro Hirano |
| 1992 | Rectification method for lookup-table type FPGA's. Yuji Kukimoto, Masahiro Fujita |
| 1992 | SHILPA: a high-level synthesis system for self-timed circuits. Venkatesh Akella, Ganesh Gopalakrishnan |
| 1992 | Synthesis fo the hardware/software interface in microcontroller-based systems. Pai H. Chou, Ross B. Ortega, Gaetano Borriello |
| 1992 | System-level routing of mixed-signal ASICs in WREN. Sujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley |
| 1992 | Test generation for delay faults in non-scan and partial scan sequential circuits. Kwang-Ting Cheng |
| 1992 | Three-phase chip planning - an improved top-down chip planning strategy. Bernd Schürmann, Joachim Altmeyer, Gerhard Zimmermann |
| 1992 | Time domain analysis of nonuniform frequency dependent high-speed interconnects. Sanjay L. Manney, Michel S. Nakhla, Qi-Jun Zhang |
| 1992 | Timing analysis in high-level synthesis. Andreas Kuehlmann, Reinaldo A. Bergamaschi |
| 1992 | Timing distribution in VHDL behavioral models. Ashish S. Gadagkar, James R. Armstrong |
| 1992 | Using constraint geometry to determine maximum rate pipeline clocking. Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah |
| 1992 | VLSI design parsing (preliminary version). Akhilesh Tyagi |
| 1992 | Valid clocking in wavepipelined circuits. William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1992 | Verification of asynchronous interface circuits with bounded wire delays. Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang |
| 1992 | Verification of systems containing counters. Enrico Macii, Bernard Plessier, Fabio Somenzi |
| 1992 | Verifying clock schedules. Thomas G. Szymanski, Narendra V. Shenoy |
| 1992 | Zero skew clock routing in multiple-clock synchronous systems. Wasim Khan, Moazzem Hossain, Naveed A. Sherwani |