| 1990 | A CAD Process Scheduling Technique. Toshiaki Miyazaki, Tamio Hoshino, Makoto Endo |
| 1990 | A Clock Net Reassignment Algorithm Usign Voronoi Diagram. Masato Edahiro |
| 1990 | A Data Flow Based Architecture for CAD Frameworks. Peter van den Hamer, Menno Treffers |
| 1990 | A Detailed Router for Field-Programmable Gate Arrays. Stephen Brown, Jonathan Rose, Zvonko G. Vranesic |
| 1990 | A Fast Algorithm for Performance-Driven Placement. Michael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh |
| 1990 | A Framework Environment for Logic Design Support System. Kaname Kuroki, Nobuyoshi Nomizu, Shigenobu Suzuki, Kazutoshi Takahashi |
| 1990 | A Global Optimization Approach for Architectural Synthesis. Catherine H. Gebotys, Mohamed I. Elmasry |
| 1990 | A Hierarchical Approach for Testing Large Circuits. Susana Stoica |
| 1990 | A Hierarchical Circuit Extractor Based on New Cell Overlap Analysis. Hirotoshi Sawada |
| 1990 | A High-Packing Density Module Generator for Bipolar Analog LSIs. Yoichi Shiraishi, Mitsuyuki Kimura, Kazuhiko Kobayashi, Tetsuro Hino, Miki Seriuchi, Manabu Kusaoke |
| 1990 | A History Model for Managing the VLSI Design Process. Tzi-cker Chiueh, Randy H. Katz |
| 1990 | A Method for Concurrent Decomposition and Factorization of Boolean Expressions. Jagadeesh Vasudevamurthy, Janusz Rajski |
| 1990 | A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-Approach. Andrew B. Kahng, Gabriel Robins |
| 1990 | A New Global Router Based on a Flow Model and Linear Assignment. G. Meixner, Ulrich Lauther |
| 1990 | A New Method for Assigning Signal Flow Directions to MOS Transistors. Kuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer |
| 1990 | A New Template Based Approach to Module Generation. John Conway, Gerard F. M. Beenker |
| 1990 | A Parallel Algorithm for Hierarchical Circuit Extraction. Krishna P. Belkhale, Prithviraj Banerjee |
| 1990 | A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations. Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern, Richard Burch, Lawrence A. Arledge Jr., Paul F. Cox |
| 1990 | A Robust Framework for Hierarchical Floorplanning with Integrated Global Wiring. Thomas Lengauer, Rolf Müller |
| 1990 | A Routing Algorithm for Harvesting Multipipeline Arrays with Small Intercell and Pipeline Delays. Peter Koo, Fabrizio Lombardi, Donatella Sciuto |
| 1990 | A Routing Methodology for Analog Integrated Circuits. Enrico Malavasi, Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli |
| 1990 | A Routing System for Mixed A/D Standard Cell LSIs. Ikuo Harada, Hitoshi Kitazawa, Takao Kaneko |
| 1990 | A Single-State-Transition Fault Model for Sequential Machines. Kwang-Ting Cheng, Jing-Yang Jou |
| 1990 | A Timing-Driven Global Router for Custom Chip Design. Somchai Prasitjutrakul, William J. Kubitz |
| 1990 | A Two-Level Two-Way Partitioning Algorithm. Yen-Chuen Wei, Chung-Kuan Cheng |
| 1990 | A Unified Framework for the Formal Verification of Sequential Circuits. Olivier Coudert, Jean Christophe Madre |
| 1990 | A Usable Circuit Optimizer for Designers. Dale E. Hocevar, Rajeev Arora, Uttiya Dasgupta, Sattam Dasgupta, Nagaraj Subramanyam, Sham Kashyap |
| 1990 | ATPG Aspects of FSM Verification. Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi |
| 1990 | AWEsim: A Program for the Efficient Analysis of Linear(ized) Circuits. Xiaoli Huang, Vivek Raghavan, Ronald A. Rohrer |
| 1990 | Accurate and Efficient Evaluation of Circuit Yield and Yield Gradients. Peter Feldmann, Stephen W. Director |
| 1990 | Algorithms for Discrete Function Manipulation. Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton |
| 1990 | An Algebra for Switch-Level Simulation. Ibrahim N. Hajj |
| 1990 | An Algorithm for Locating Logic Design Errors. Masahiro Tomita, Hong-Hai Jiang, Tamotsu Yamamoto, Yoshihiro Hayashi |
| 1990 | An Algorithm for Nearly-Minimal Collapsing of Finite-State Machine Networks. Wayne H. Wolf |
| 1990 | An Automata-Theoretic Approach to Behavioral Equivalence. Srinivas Devadas, Kurt Keutzer |
| 1990 | An Exact Algorithm for Single-Layer Wire-Length Minimization. Jan-Ming Ho, Majid Sarrafzadeh, Atsushi Suzuki |
| 1990 | An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. Yusuf Leblebici, Sung-Mo Kang |
| 1990 | An O( Se-Kyoung Hong, In-Cheol Park, Chong-Min Kyung |
| 1990 | An Optimal Channel Pin Assignment Algorithm. Yang Cai, D. F. Wong |
| 1990 | Analysis of High-Speed VLSI Interconnects Using the Asymptotic Waveform Evaluation Technique. Tak K. Tang, Michel S. Nakhla |
| 1990 | Analysis of VLSI Microconductor Systems by Bi-Level Waveform Relaxation. Rui Wang, Omar Wing |
| 1990 | Automatic High Level Syntesis of Partitioned Busses. Christian Ewering |
| 1990 | Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda |
| 1990 | CADICS - Cyclic Analog-to-Digital Converter Synthesis. Gani Jusuf, Paul R. Gray, Alberto L. Sangiovanni-Vincentelli |
| 1990 | Circuit Simulation Algorithms on a Distributed Memory Multiprocessor System. John A. Trotter, Prathima Agrawal |
| 1990 | Computing Parametric Yield Accurately and Efficiently. Linda Milor, Alberto L. Sangiovanni-Vincentelli |
| 1990 | Computing the Error Escape Probability in Count-Based Compaction Schemes. André Ivanov, Yervant Zorian |
| 1990 | Congestion-Driven Placement Using a New Multi-Partitioning Heuristic. Stefan Mayrhofer, Ulrich Lauther |
| 1990 | Constraint Identification for Timing Verification. Joel Grodstein, Jengwei Pan, William J. Grundmann, Bruce Gieseke, Yao-Tsung Yen |
| 1990 | Constraint-Based Channel Routing for Analog and Mixed Analog/Digital Circuits. Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli |
| 1990 | Contest: A Fast ATPG Tool for Very Large Combinatorial Circuits. Udo Mahlstedt, Torsten Grüning, Cengiz Özcan, Wilfried Daehn |
| 1990 | DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation. Douglas R. Holberg, Santanu Dutta, Lawrence T. Pillage |
| 1990 | Data Path Construction and Refinement. Fur-Shing Tsai, Yu-Chin Hsu |
| 1990 | Design for Circuit Quality: Yield Maximization, Minimax, and Taguchi Approach. M. A. Styblinski |
| 1990 | Diffusion - An Analytic Procedure Applied to Macro Cell Placement. Chong-Min Kyung, Peter V. Kraus, Dieter A. Mlynski |
| 1990 | Distributed Methodology Management for Design-in-the-Large. Wayne Allen, Douglas Rosenthal, Kenneth W. Fiduk |
| 1990 | Don't Care Minimization of Multi-Level Sequential Logic Networks. Bill Lin, Hervé J. Touati, A. Richard Newton |
| 1990 | Efficient Automatic Diagnosis of Digital Circuits. Heh-Tyan Liaw, Jia-Horng Tsaih, Chen-Shang Lin |
| 1990 | Efficient Pole Zero Sensitivity Calculation in AWE. John Y. Lee, Xiaoli Huang, Ronald A. Rohrer |
| 1990 | Evaluation and Synthesis of Self-Monitoring State Machines. Scott H. Robinson, John Paul Shen |
| 1990 | Exploitation of Periodicity in Logic Simulation of Synchronous Circuits. Rahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich |
| 1990 | Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis. D. L. Springer, Donald E. Thomas |
| 1990 | Extraction of Functional Information from Combinatorial Circuits. M. Ohmura, Hiroto Yasuura, Keikichi Tamaru |
| 1990 | FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate Arrays. Masako Murofushi, Masaaki Yamada, Takashi Mitsuhashi |
| 1990 | Fast Overlapped Scattered Array Storage Schemes for Sparse Matrices. John A. Trotter, Prathima Agrawal |
| 1990 | Fast Switch-Level Fault Simulation Using Functional Fault Modeling. Evstratios Vandris, Gerald E. Sobelman |
| 1990 | Feedback-Driven Datapath Optimization in Fasolt. David Knapp |
| 1990 | Finding Clusters in VLSI Circuits. Jörn Garbers, Hans Jürgen Prömel, Angelika Steger |
| 1990 | Floorplanning by Topological Constraint Reduction. Gopalakrishnan Vijayan, Ren-Song Tsay |
| 1990 | Floorplanning with Pin Assignment. Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh |
| 1990 | GRCA: A Global Approach for Floorplanning Synthesis in VLSI Macrocell Design. Alexander Herrigel |
| 1990 | HS: A Hierarchical Search Package for CAD Data. Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu |
| 1990 | High-Level Delay Estimation for Technology-Independent Logic Equations. David E. Wallace, Mandalagiri S. Chandrasekhar |
| 1990 | IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers |
| 1990 | Implicit State Enumeration of Finite State Machines Using BDDs. Hervé J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
| 1990 | Incorporation of Inductors in Piecewise Approximate Circuit Simulation. Chandramouli Visweswariah, Peter Feldmann, Ronald A. Rohrer |
| 1990 | Knowledge Based Design Flow Management. Felix Bretschneider, Christa Kopf, Helmut Lagger, Arding Hsu, Elizabeth Wei |
| 1990 | Logic Compilation from Graphical Dependency Notation. Jukka Lahti, Jorma Kivelä |
| 1990 | Logic Simulation and Parallel Processing. Vishwani D. Agrawal, Srimat T. Chakradhar |
| 1990 | MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | MOSP: Module Selection for Pipelined Designs with Multi-Cycle Operations. Rajiv Jain |
| 1990 | Measuring Error Propagation in Waveform Relaxation Algorithms. Charles A. Zukowski, George Gristede, Albert E. Ruehli |
| 1990 | Minimization of Symbolic Relations. Bill Lin, Fabio Somenzi |
| 1990 | Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm. Chun-Hung Chen, Jacob A. Abraham |
| 1990 | Mixed-Mode Incremental Simulation and Concurrent Fault Simulation. Yun-Cheng Ju, Fred L. Yang, Resve A. Saleh |
| 1990 | Multi-Level Logic Minimization Across Latch Boundaries. Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda |
| 1990 | Multi-Level Optimization for Large Scale ASICS. Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura |
| 1990 | New Algorithms for the Placement and Routing of Macro Cells. William Swartz, Carl Sechen |
| 1990 | Observability Don't Care Sets and Boolean Relations. Maurizio Damiani, Giovanni De Micheli |
| 1990 | On Determining Scan Flip-Flops in Partial-Scan Designs. Dong-Ho Lee, Sudhakar M. Reddy |
| 1990 | On the Diagnostic Resolution of Signature Analysis. Janusz Rajski, Jerzy Tyszer, Babak Salimi |
| 1990 | On the Efficiency of the Transition Fault Model for Delay Faults. Manfred Geilert, Jürgen Alt, Michael Zimmermann |
| 1990 | Optimal Orientations of Transistor Chains. T. W. Her, D. F. Wong, T. H. Freeman |
| 1990 | Optimal Test Set Design for Analog Circuits. Linda Milor, Alberto L. Sangiovanni-Vincentelli |
| 1990 | Optimization of the Parallel Technique for Compiled Unit-Delay Simulation. Peter M. Maurer |
| 1990 | Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications. Peter Vanbekbergen, Francky Catthoor, Gert Goossens, Hugo De Man |
| 1990 | PHIFACT, a Boolean Preprocessor for Multi-Level Logic Synthesis. F. Crowet, Marc Davio, C. Dierieck, J. Durieu, G. Louis, Chantal Ykman-Couvreur |
| 1990 | Parallel Simulation Algorithms for Grid-Based Analog Signal Processors. Luís Miguel Silveira, Andrew Lumsdaine, Jacob White |
| 1990 | Partial Detectability Profiles. Paul G. Ryan, W. Kent Fuchs |
| 1990 | Partial Scan by Use of Empirical Testability. Kee Sup Kim, Charles R. Kime |
| 1990 | Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. Allen C.-H. Wu, Daniel Gajski |
| 1990 | Partitioning of Functional Models of Synchronous Digital Systems. Rajesh K. Gupta, Giovanni De Micheli |
| 1990 | Performance Optimization of Pipelined Circuits. Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1990 | Preform: A Process Independent Symbolic Layout System. Jean-Claude Dufourd, Jean-François Naviner, Francis Jutand |
| 1990 | QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults. Weiwei Mao, Ravi K. Gulati, Deepak K. Goel, Michael D. Ciletti |
| 1990 | Race Detection for Two-Phase Systems. Joel Grodstein, Jim Montanaro, Susanne Marino |
| 1990 | Rectilinear Steiner Tree Construction by Local and Global Refinement. Ting-Hai Chao, Yu-Chin Hsu |
| 1990 | Rubber Band Routing and Dynamic Data Representation. Wayne Wei-Ming Dai, Raymond Kong, Jeffrey Jue |
| 1990 | SALSA: A New Approach to Scheduling with Timing Constraints. John A. Nestor, Ganesh Krishnamoorthy |
| 1990 | SIMCURRENT: An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits. Ulrich Jagau |
| 1990 | SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. David T. Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham |
| 1990 | Simulating Electromagnetic Radiation of Printed Circuit Boards. Hansruedi Heeb, Albert E. Ruehli, J. Janak, Shahrokh Daijavad |
| 1990 | Tautology Checking Using Cross-Controllability and Cross-Observability Relations. Eduard Cerny, C. Mauras |
| 1990 | Test Vector Minimization During Logic Synthesis. Tsu-Wei Ku, Wei-Kong Chia |
| 1990 | Testability-Preserving Circuit Transformations. Michael J. Bryan, Srinivas Devadas, Kurt Keutzer |
| 1990 | The Component Sythesis Algorithm: Technology Mapping for Register Transfer Descriptions. Elke A. Rundensteiner, Daniel Gajski, Lubomir Bic |
| 1990 | Three-Dimensional Routing for Multilayer Ceramic Printed Circuit Boards. Akihiko Hanafusa, Yasuhiro Yamashita, Mitsuru Yasuda |
| 1990 | Timing Constraints for Correct Performance. Habib Youssef, Eugene Shragowitz |
| 1990 | Timing Optimization with Testability Considerations. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng |
| 1990 | Topological Routing Using Geometric Information. Shinichiro Haruyama, D. F. Wong, Donald S. Fussell |
| 1990 | Touch and Cross Router. Kaoru Kawamura, Tatsuya Shindo, Toshiyuki Shibuya, Hideki Miwatari, Yoshie Ohki |
| 1990 | VLSI Placement Using Uncertain Costs. Cheryl Harkness, Daniel P. Lopresti |
| 1990 | XREF/COUPLING: Capacitive Coupling Error Checker. William J. Grundmann, Yao-Tsung Yen |