| 1989 | 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers |
| 1989 | A Newton waveform relaxation algorithm for circuit simulation. Donald J. Erdman, Donald J. Rose |
| 1989 | A bounded delay race model. Carl-Johan H. Seger |
| 1989 | A clock distribution scheme for nonsymmetric VLSI circuits. Parameswaran Ramanathan, Kang G. Shin |
| 1989 | A custom cell generation system for double-metal CMOS technology. P. Gee, Ibrahim N. Hajj, Sung-Mo Kang |
| 1989 | A data management interface as part of the framework of an integrated VLSI-design system. Ernst Siepmann |
| 1989 | A data model and architecture for VLSI/CAD databases. Anoop Singhal, Nishit P. Parikh, Debaprosad Dutt, Chi-Yuan Lo |
| 1989 | A diagnosis method using pseudo-random vectors without intermediate signatures. Robert C. Aitken, Vinod K. Agarwal |
| 1989 | A layout defect-sensitivity extractor. José Pineda de Gyvez, Jochen A. G. Jess |
| 1989 | A logic synthesis system for VHDL design descriptions. Thomas E. Dillinger, Kathy M. McCarthy, Thomas A. Mosher, Dale R. Neumann, Randall A. Schmidt |
| 1989 | A manufacturing-oriented environment for synthesis of fabrication processes. John S. Wenstrand, Hiroshi Iwai, Robert W. Dutton |
| 1989 | A minimum separation algorithm for river routing with bounded number of jogs. Andranik Mirzaian |
| 1989 | A model for comparing synchronization strategies for parallel logic-level simulation. Mary L. Bailey, Lawrence Snyder |
| 1989 | A new approach to optimal cell synthesis. Jan Madsen |
| 1989 | A new approach to sea-of-gates global routing. Tai-Ming Parng, Ren-Song Tsay |
| 1989 | A new integer linear programming formulation for the scheduling problem in data path synthesis. Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin |
| 1989 | A new methodology for the design centering of IC fabrication processes. K. K. Low, Stephen W. Director |
| 1989 | A novel reconfiguration scheme for 2-D processor arrays. Phill-Kyu Rhee, Jung Hwan Kim, Hee Yong Youn |
| 1989 | A powerful global router: based on Steiner min-max trees. Charles C. Chiang, Majid Sarrafzadeh, Chak-Kuen Wong |
| 1989 | A resource sharing and control synthesis method for conditional branches. Kazutoshi Wakabayashi, Takeshi Yoshimura |
| 1989 | A table look-up model using a 3-D isoparametric shape function with improved convergency. Dae-Hyung Cho, Tae-Han Kim, Jeong-Taek Kong |
| 1989 | A timing model for static CMOS gates. Hau-Yung Chen, Santanu Dutta |
| 1989 | AGAR: a single-layer router for gate array cell generation. Mark A. Mostow |
| 1989 | Accurate logic simulation in the presence of unknowns. Susheel J. Chandra, Janak H. Patel |
| 1989 | An O(n log n) algorithm for 1-D tile compaction. Richard Anderson, Simon Kahan, Martine D. F. Schlag |
| 1989 | An accurate timing model for fault simulation in MOS circuits. Sungho Kim, Prithviraj Banerjee |
| 1989 | An algorithm for hierarchical floorplan design. D. F. Wong, Khe-Sing The |
| 1989 | An approach for the yield enhancement of programmable gate arrays. Vijay P. Kumar, Anton T. Dahbura, Fred Fischer, Patrick Juola |
| 1989 | An efficient algorithm for layout compaction problem with symmetry constraints. R. Okuda, Takashi Sato, Hidetoshi Onodera, K. Tamariu |
| 1989 | An efficient channel routing algorithm for defective arrays. Hee Yong Youn, Adit D. Singh |
| 1989 | An efficient method for parametric yield optimization of MOS integrated circuits. Tat-Kwan Yu, Sung-Mo Kang, Jerome Sacks, William J. Welch |
| 1989 | An exact minimizer for Boolean relations. Robert K. Brayton, Fabio Somenzi |
| 1989 | An optimal transistor-chaining algorithm for CMOS cell layout. Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu |
| 1989 | Analogue circuit optimization in a graphical environment. Paul J. Rankin, J. M. Siemensma |
| 1989 | Arithmetic and galois checksums. Nirmal R. Saxena, Edward J. McCluskey |
| 1989 | Automatic mixed-mode timing simulation. David Overhauser, Ibrahim N. Hajj, Yi-Fan Hsu |
| 1989 | Automating the diagnosis and the rectification of design errors with PRIAM. Jean Christophe Madre, Olivier Coudert, Jean-Paul Billon |
| 1989 | Boolean minimization and algebraic factorization procedures for fully testable sequential machines. Srinivas Devadas, Kurt Keutzer |
| 1989 | C3DSTAR: a 3D wiring capacitance calculator. James Janak, David D. Ling, Hao-Ming Huang |
| 1989 | CETUS-a versatile custom cell synthesizer. P. K. Sun |
| 1989 | CLEO: a CMOS layout generator. Antun Domic, Samuel Levitin, Nathan Phillips, Channeary Thai, Thomas R. Shiple, Dilip Bhavsar, Clint Bissel |
| 1989 | CRACKER: a general area router based on stepwise reshaping. Sabih H. Gerez, Otto E. Herrmann |
| 1989 | Combining partitioning and global routing in sea-of-cells design. Bernhard Korte, Hans Jürgen Prömel, Angelika Steger |
| 1989 | Computation of bus current variance for reliability estimation of VLSI circuits. Farid N. Najm, Ibrahim N. Hajj, Ping Yang |
| 1989 | Consistency and observability invariance in multi-level logic synthesis. Patrick C. McGeer, Robert K. Brayton |
| 1989 | Constrained floorplan design for flexible blocks. Sai-keung Dong, Jason Cong, C. L. Liu |
| 1989 | Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree. Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong |
| 1989 | Critical path issue in VLSI design. Habib Youssef, Eugene Shragowitz, Lionel Bening |
| 1989 | DEC's engineering to manufacturing BRIDGE system based on the D-BUS architecture. Richard J. Bonneau |
| 1989 | Definition and assignment of complex data-paths suited for high throughput applications. Stefaan Note, Francky Catthoor, Jef L. van Meerbergen, Hugo De Man |
| 1989 | Design of sequential machines for efficient test generation. Kwang-Ting Cheng, Vishwani D. Agrawal |
| 1989 | Dynamic redundancy identification in automatic test generation. Miron Abramovici, David T. Miller, Rabindra K. Roy |
| 1989 | Early matching of system requirements and package capabilities. David P. LaPotin, Y.-H. Chen |
| 1989 | Event-EMU: an event driven timing simulator for MOS VLSI circuits. Bryan D. Ackland, Robert A. Clark |
| 1989 | Exact critical path tracing fault simulation on massively parallel processor AAP2. Yoshihiro Kitamura |
| 1989 | FACT-a testability analysis methodology. Thirumalai Sridhar |
| 1989 | FANHAT: fanout oriented hierarchical automatic test generation system. Hyoung B. Min, William A. Rogers, Hwei-Tsu Ann Luh |
| 1989 | FDT-a design tool for switched capacitor filters. Sattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild |
| 1989 | Fast incremental netlist compilation of hierarchical schematics. Larry G. Jones |
| 1989 | Fast test generation for sequential circuits. Todd P. Kelsey, Kewal K. Saluja |
| 1989 | Fast two-level logic minimizers for multi-level logic synthesis. Hamid Savoj, Abdul A. Malik, Robert K. Brayton |
| 1989 | Fault detection and location in reconfigurable VLSI arrays. Kuochen Wang, Sy-Yen Kuo |
| 1989 | Fault detection in a testable PLA with low overhead for production testing. Yi-Nan Shen, Fabrizio Lombardi |
| 1989 | Functional comparison of logic designs for VLSI circuits. C. Leonard Berman, Louise Trevillyan |
| 1989 | Global refinement for building block layout. Ying-Meng Li, Pushan Tang |
| 1989 | HAM-a hardware accelerator for multi-layer wire routing. Raja Venkateswaran, Pinaki Mazumder |
| 1989 | Hierarchical compiled event-driven logic simulation. David M. Lewis |
| 1989 | High performance test generation for accurate defect models in CMOS gate array technology. Hector R. Sucar, Susheel J. Chandra, David J. Wharton |
| 1989 | High-speed compiled-code simulation of transition faults. Manfred Geilert |
| 1989 | Inserting active delay elements to achieve wave pipelining. Derek C. Wong, Giovanni De Micheli, Michael J. Flynn |
| 1989 | Interconnection length estimation for optimized standard cell layouts. Massoud Pedram, Bryan Preas |
| 1989 | LADIES: an automatic layout system for analog LSI's. Masato Mogaki, Naoki Kato, Youko Chikami, Naoyuki Yamada, Yasuhiro Kobayashi |
| 1989 | Layout methods for digital optical computing. Miles Murdocca |
| 1989 | Layout-driven test generation. Phil Nigh, Wojciech Maly |
| 1989 | Manual rescheduling and incremental repair of register-level datapaths. David W. Knapp |
| 1989 | Mixed-mode simulation of compiled VHDL programs. Ramón D. Acosta, Steven P. Smith, Jeff Larson |
| 1989 | Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation. Peter R. O'Brien, Thomas L. Savarino |
| 1989 | Modeling uncertainty in RC timing analysis. Cheryl Harkness, Daniel P. Lopresti |
| 1989 | Module assignment and interconnect sharing in register-transfer synthesis of pipelined data paths. Nohbyung Park, Fadi J. Kurdahi |
| 1989 | Multi-level logic optimization using binary decision diagrams. Yusuke Matsunaga, Masahiro Fujita |
| 1989 | Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout. Wing K. Luk, Alvar A. Dean, John W. Mathews |
| 1989 | New ATPG techniques for logic optimization. Reily M. Jacoby, P. Moceyunas, Hyunwoo Cho, Gary D. Hachtel |
| 1989 | On optimal extraction of combinational logic and don't care sets from hardware description languages. Glenn Colón-Bonet, Eric M. Schwarz, D. G. Bostick, Gary D. Hachtel, Michael R. Lightner |
| 1989 | On properties of algebraic transformation and the multifault testability of multilevel logic. Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison |
| 1989 | On the computation of the ranges of detected delay fault sizes. Ankan K. Pramanick, Sudhakar M. Reddy |
| 1989 | Optimal granularity of test generation in a distributed system. Hideo Fujiwara, Tomoo Inoue |
| 1989 | Optimal layout via Boolean satisfiability. Srinivas Devadas |
| 1989 | Optimal wafer probe testing and diagnosis of k-out-of-n structures. Ming-Feng Chang, Weiping Shi, W. Kent Fuchs |
| 1989 | Optimum and heuristic algorithms for finite state machine decomposition and partitioning. Pranav Ashar, Srinivas Devadas, A. Richard Newton |
| 1989 | PACE2: an improved parallel VLSI extractor with parameter extraction. Krishna P. Belkhale, Prithviraj Banerjee |
| 1989 | PGS and PLUCGS-two new matrix solution techniques for general circuit simulation. Richard Burch, Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang, Paul F. Cox |
| 1989 | PLA decomposition with generalized decoders. Seiyang Yang, Maciej J. Ciesielski |
| 1989 | Piecewise approximate circuit simulation. Chandramouli Visweswariah, Ronald A. Rohrer |
| 1989 | Pin assignment with global routing. Jason Cong |
| 1989 | Portable parallel logic and fault simulation. Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham |
| 1989 | Practicality of state-machine verification of speed-independent circuits. Steven M. Nowick, David L. Dill |
| 1989 | Restricted symbolic evaluation is fast and useful. J. Lawrence Carter, Barry K. Rosen, Gordon L. Smith, Vijay Pitchumani |
| 1989 | Routing using a pyramid data structure. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai |
| 1989 | SLIP: a software environment for system level interactive partitioning. Mark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton |
| 1989 | SPECS simulation validation with efficient transient sensitivity computation. Tuyen V. Nguyen, Peter Feldmann, Stephen W. Director, Ronald A. Rohrer |
| 1989 | SYLON-DREAM: a multi-level network synthesizer. Kuang-Chien Chen, Saburo Muroga |
| 1989 | Scheduling and hardware sharing in pipelined data paths. Ki Soo Hwang, Albert E. Casavant, Ching-Tang Chang, Manuel A. d'Abreu |
| 1989 | Specification and verification of VLSI systems. Asher Wilk, Amir Pnueli |
| 1989 | State assignment for initializable synthesis (gate level analysis). Kwang-Ting Cheng, Vishwani D. Agrawal |
| 1989 | State assignment for multilevel logic using dynamic literal estimation. Michael Bolotski, Daniel Camporese, Rod Barman |
| 1989 | Statistical bipolar circuit design using MSTAT. Nicolas Salamina, Mark R. Rencher |
| 1989 | Structure optimization in logic schematic generation. Tsung D. Lee, Lawrence P. McNamee |
| 1989 | Switch-level VHDL descriptions. Alec G. Stanculescu, Andy S. Tsay, Alex N. D. Zamfirescu, D. L. Perry |
| 1989 | Synthesis of address generators. Douglas M. Grant, Peter B. Denyer, I. Finlay |
| 1989 | Synthesis of delay fault testable combinational logic. Kaushik Roy, Jacob A. Abraham, Kaushik De, Stephen L. Lusky |
| 1989 | TIGER: testability insertion guidance expert system. Magdy S. Abadir |
| 1989 | Test generation for highly sequential circuits. Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
| 1989 | The EVE VLSI information management environment. Hamideh Afsarmanesh, Esther Brotoatmodjo, Kwang June Byeon, Alice C. Parker |
| 1989 | The Stickizer: a layout to symbolic converter. Jean-Claude Dufourd |
| 1989 | The critical path for multiple faults. Samy Makar, Edward J. McCluskey |
| 1989 | Thermal analysis in SPICE. Rao Prakash Pokala, Dileep A. Divekar |
| 1989 | Timing driven placement. Malgorzata Marek-Sadowska, Shen Lin |
| 1989 | Timing models in VAL/VHDL. Larry M. Augustin |
| 1989 | Towards efficient hierarchical designs by ratio cut partitioning. Yen-Chuen Wei, Chung-Kuan Cheng |
| 1989 | Translating concurrent programs into delay-insensitive circuits. Erik Brunvand, Robert F. Sproull |
| 1989 | Tree-height minimization in pipelined architectures. Richard I. Hartley, Albert E. Casavant |
| 1989 | Two-dimensional compaction for placement refinement. Xiao-Ming Xiong |
| 1989 | Uninterpreted modeling using the VHSIC hardware description language (VHDL). F. T. Hady, James H. Aylor, Ronald D. Williams, Ronald Waxman |
| 1989 | VHDL modeling for analog-digital hardware designs (VHSIS hardware description language). Balsha R. Stanisic, Mark W. Brown |
| 1989 | Waveform relaxation for transient simulation of two-dimensional MOS devices. Mark W. Reichelt, Jacob K. White, Jonathan Allen |
| 1989 | WireLisp: combining graphics and procedures in a circuit specification language. Carl Ebeling, Zhanbing Wu |
| 1989 | Yoda: a framework for the conceptual design VLSI systems. Allen M. Dewey, Stephen W. Director |