| 1988 | 1988 IEEE International Conference on Computer-Aided Design, ICCAD 1988, Santa Clara, CA, USA, November 7-10, 1988. Digest of Technical Papers |
| 1988 | A band relaxation algorithm for reliable and parallelizable circuit simulation. Andrew Lumsdaine, Jacob White, Donald M. Webber, Alberto L. Sangiovanni-Vincentelli |
| 1988 | A detailed router based on simulated evolution. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai |
| 1988 | A dormant subcircuit model for maximizing iteration latency. Paul F. Cox, Richard Burch, Ping Yang |
| 1988 | A fast algorithm for the optimal state assignment of large finite state machines. Devadas Varma, Eliezer A. Trachtenberg |
| 1988 | A fast fault simulation algorithm for combinational circuits. Wuudiann Ke, Sharad C. Seth, Bhargab B. Bhattacharya |
| 1988 | A fault simulation method based on stem regions. Fadi Maamari, Janusz Rajski |
| 1988 | A grid generation system for process and device simulation. Akio Yajima, Hirofumi Jonishi, Akihisa Maruyama |
| 1988 | A linear-time Steiner tree routing algorithm for terminals on the boundary of a rectangle. James P. Cohoon, Dana S. Richards, Jeffrey S. Salowe |
| 1988 | A method for net representation with polygon decomposition. Chun-Ping George Chi |
| 1988 | A modified approach to two-level logic minimization. Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
| 1988 | A new algorithm for CMOS gate matrix layout. C. Y. Roger Chen, Cliff Yungchin Hou |
| 1988 | A new algorithm for standard cell global routing. Jinepheng Cong, Bryan Preas |
| 1988 | A new algorithm for topological routing and via minimization. Xiao-Ming Xiong |
| 1988 | A new formulation of yield enhancement problems for reconfigurable chips. Nany Hasan, Jason Cong, C. L. Liu |
| 1988 | A new global router for row-based layout. Kai-Win Lee, Carl Sechen |
| 1988 | A new layout optimization methodology for CMOS complex gates. C. Y. Roger Chen, Cliff Yungchin Hou |
| 1988 | A new method for the efficient state-assignment of PLA-based sequential machines. José L. Huertas, José M. Quintana |
| 1988 | A submicron MOSFET model for simulation of analog circuits. Abhijit Chatterjee, Charles F. Machala III, Ping Yang |
| 1988 | A symbolic analysis tool for analog circuit design automation. Steven J. Seda, Marc G. R. Degrauwe, Wolfgang Fichtner |
| 1988 | A table look-up MOSFET model for analog applications. Phillip E. Allen, Kwang S. Yoon |
| 1988 | A tabular macromodeling approach to fast timing simulation including parasitics. David Overhauser, Ibrahim N. Hajj |
| 1988 | A tool for hierarchical test generation. Gerd Krüger |
| 1988 | Aliasing probability of non-exhaustive randomized syndrome tests. Robert C. Aitken, Vinod K. Agarwal |
| 1988 | An efficient compaction algorithm for test vectors of microprocessors and microcontrollers. Ravi K. Gulati, Deepak K. Goel |
| 1988 | An efficient macromodeling approach for statistical IC process design. K. K. Low, Stephen W. Director |
| 1988 | An efficient method for circuit sensitivity calculation using piecewise linear waveform models. Sung-Mo Kang, Yusuf Leblebici |
| 1988 | An efficient sequential range query model for minimum width/space verification (circuit analysis). J. C. Jeong, S. Y. Shin, C. D. Lee, Y. U. Yu |
| 1988 | An envelope-following method for the efficient transient simulation of switching power and filter circuits. Kenneth S. Kundert, Jacob White, Alberto L. Sangiovanni-Vincentelli |
| 1988 | An improved objective function for mincut circuit partitioning. Carl Sechen, Dahe Chen |
| 1988 | Analog circuit synthesis for performance in OASYS. Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley |
| 1988 | Area-time model for synthesis of non-pipelined designs. Rajiv Jain, Mitch J. Mlinar, Alice C. Parker |
| 1988 | Automatic layout generation for CMOS operational amplifiers. Han Young Koh, Carlo H. Séquin, Paul R. Gray |
| 1988 | Automatic layout of custom analog cells in ANAGRAM. David J. Garrod, Rob A. Rutenbar, L. Richard Carley |
| 1988 | Automatic modeling of switch-level networks using partial orders. Prathima Agrawal, Scott H. Robinson, Thomas G. Szymanski |
| 1988 | Automatic synthesis and technology mapping of combinational logic. Reinaldo A. Bergamaschi |
| 1988 | Automatic synthesis of a multi-bus architecture for DSP. Baher Haroun, Mohamed I. Elmasry |
| 1988 | Automatic test generation using neural networks. Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal |
| 1988 | Automatically extracting structure from a logical design. Mark Hirsch, Daniel P. Siewiorek |
| 1988 | BEATNP: a tool for partitioning Boolean networks. Hyunwoo Cho, Gary D. Hachtel, M. Nash, L. Setiono |
| 1988 | Bisim: a simulator for custom ECL circuits. Russell Kao, Bob Alverson, Mark Horowitz, Don Stark |
| 1988 | Boolean decomposition in multi-level logic optimization. Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
| 1988 | Built-in current testing-feasibility study. Wojciech Maly, Phil Nigh |
| 1988 | Built-in self-test for large embedded CMOS folded PLAs. Ramaswami Dandapani, Ravi K. Gulati, Deepak K. Goel |
| 1988 | CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits. Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Jacob A. Abraham, Joseph T. Rahmeh |
| 1988 | CLANS: a high-level synthesis tool for high resolution data converters. John G. Kenney, L. Richard Carley |
| 1988 | CLAY: a malleable-cell multi-cell transistor matrix approach for CMOS LAYout synthesis. Paul Kollaritsch, Steve Lusky, Sharat Prasad, Neil Potter |
| 1988 | CMOS inverter delay and other formulas using alpha -power law MOS model. Takayasu Sakurai |
| 1988 | CODECS: a fixed mixed-level device and circuit simulator. Kartikeya Mayaram, Donald O. Pederson |
| 1988 | CREST-a current estimator for CMOS circuits. Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj |
| 1988 | Carioca-A 'smart' and flexible switch-box router. Pierre-François Dubois, Alain Puissochet, Anne-Marie Tagant |
| 1988 | Cbase 1.0: a CAD database for VLSI circuits using object oriented technology. Melvin A. Breuer, Wesley H. Cheng, Rajiv Gupta, Ido Hardonag, Ellis Horowitz, S. Y. Lin |
| 1988 | Channel routing order for building-block layout with rectilinear modules. Mohankumar Guruswamy, Martin D. F. Wong |
| 1988 | Codar: a congestion-directed general area router. Pin-San Tzeng, Carlo H. Séquin |
| 1988 | Combining circuit level changes with electrical optimization. Fred W. Obermeier, Randy H. Katz |
| 1988 | Combining event and data-flow graphs in behavioral synthesis. Gaetano Borriello |
| 1988 | Compaction of ATPG-generated test sequences for sequential circuits. Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh |
| 1988 | Constrained conditional resource sharing in pipeline synthesis. Ki Soo Hwang, Albert E. Casavant, Martin Dragomirecky, Manuel A. d'Abreu |
| 1988 | Critical path tracing in sequential circuits. Prem R. Menon, Ytzhak H. Levendel, Miron Abramovici |
| 1988 | Current estimation in MOS IC logic circuits. S. Chowdhury, Javed Sabir Barkatullah |
| 1988 | Data parallel switch-level simulation. Randal E. Bryant |
| 1988 | Decomposition and factorization of sequential finite state machines. Srinivas Devadas, A. Richard Newton |
| 1988 | Delay computation in switch-level models of non-treelike MOS circuits. Denis Martin, Nicholas C. Rumin |
| 1988 | Diagnosis and repair of memory with coupling faults. Ming-Feng Chang, W. Kent Fuchs, Janak H. Patel |
| 1988 | Discrete-event simulation on hypercube architectures. Roger D. Chamberlain, Mark A. Franklin |
| 1988 | Don't cares and global flow analysis of Boolean networks. Robert K. Brayton, Ellen M. Sentovich, Fabio Somenzi |
| 1988 | Doubly folded transistor matrix layout. Lukas P. P. P. van Genneken, Jos T. J. van Eijndhoven, Jos A. H. C. M. Brouwers |
| 1988 | ECSTASY: a new environment for IC design optimization. Jyuo-Min Shyu, Alberto L. Sangiovanni-Vincentelli |
| 1988 | Efficient handling of large wiring data in TANGATE. Tom Kronmiller |
| 1988 | Evaluation and improvement of Boolean comparison method based on binary decision diagrams. Masahiro Fujita, Hisanori Fujisawa, Nobuaki Kawato |
| 1988 | Expanded rectangles: a new VLSI data structure. Michael Quayle, Jon A. Solworth |
| 1988 | Experiments in logic optimization. Michael R. Lightner, Wayne H. Wolf |
| 1988 | First order nonlinear device bypass in circuit simulation. Bill Nye |
| 1988 | Flexible module generation in the FACE design environment. William D. Smith, Jeffrey R. Jasica, Michael J. Hartman, Manuel A. d'Abreu |
| 1988 | Floorplan design using distributed genetic algorithms. James P. Cohoon, Shailesh U. Hegde, Worthy N. Martin, Dana Richards |
| 1988 | GORDIAN: a new global optimization/rectangle dissection method for cell placement. Jürgen M. Kleinhans, Georg Sigl, Frank M. Johannes |
| 1988 | Gate matrix partitioning. Shuo Huang, Omar Wing |
| 1988 | GeminiII: a second generation layout validation program. Carl Ebeling |
| 1988 | Hierarchical placement for macrocells: a 'meet in the middle' approach. Bernhard Eschermann, Wayne Wei-Ming Dai, Ernest S. Kuh, Massoud Pedram |
| 1988 | Hill climbing with reduced search space (logic optimization). Daniel Brand |
| 1988 | Improved logic optimization using global flow analysis. C. Leonard Berman, Louise Trevillyan |
| 1988 | Input assignment algorithm for decoded-PLAs with multi-input decoders. Kuang-Chien Chen, Saburo Muroga |
| 1988 | Logic simulation on vector processors. Ram Raghavan, John P. Hayes, William R. Martin |
| 1988 | Logic verification using binary decision diagrams in a logic synthesis environment. Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1988 | M Rakesh Chadha, Chin-Fu Chen |
| 1988 | Modeling and enhancing virtual memory performance in logic simulation. S. P. Smith, J. Kuban |
| 1988 | MulCh: a multi-layer channel router using one, two, and three layer partitions. Ronald I. Greenberg, Alexander T. Ishii, Alberto L. Sangiovanni-Vincentelli |
| 1988 | NCUBE: an automatic test generation program for iterative logic arrays. Abhijit Chatterjee, Jacob A. Abraham |
| 1988 | NOISY: an electrical noise checker for ULSI. F. Gourdy, Alain Greiner, M. Guillemet, Roland Marbot, J. Murzin |
| 1988 | Net characterization based channel router: FT router. H. Zhu, Robert H. Fujii |
| 1988 | On the design of robust multiple fault testable CMOS combinational logic circuits. Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha |
| 1988 | Optimal CMOS cell transistor placement: a relaxation approach. André Stauffer, Ravi Nair |
| 1988 | Over-the-cell channel routing. Jingsheng Cong, C. L. Liu |
| 1988 | PACE: a parallel VLSI extractor on the Intel hypercube multiprocessor. Krishna P. Belkhale, Prithviraj Banerjee |
| 1988 | PLA optimization using output encoding. Alexander Saldanha, Randy H. Katz |
| 1988 | PYRAMID-a hierarchical waveform relaxation-based circuit simulation program. Peter Saviz, Omar Wing |
| 1988 | Parallel PLA fault simulation based on Boolean vector operations. Eli Chiprout, Janusz Rajski, Markus Robinson |
| 1988 | Parallel logic/fault simulation of VLSI array logic. Pradip Bose |
| 1988 | Parallel polygon operations using loosely coupled workstations. Rod D. W. Widdowson, Kenny Ferguson |
| 1988 | Partitioning issues in circuit simulation on multiprocessors. David C. Yeh, Vasant B. Rao |
| 1988 | Performance enhancements in BOLD using 'implications'. Gary D. Hachtel, Reily M. Jacoby, P. Moceyunas, Christopher R. Morrison |
| 1988 | Predictive subset testing for IC performance. Jay B. Brockman, Stephen W. Director |
| 1988 | Simulated annealing: a fast heuristic for some generic layout problems. Jimmy Lam, Jean-Marc Delosme |
| 1988 | Simulating mixed analog-digital circuits on a digital simulator. Donald Thelen, John Macdonald |
| 1988 | Stick diagram extraction program SKELETON. Masayuki Sato, Noriaki Ohba, Hiromi Watanabe, Shozo Saito |
| 1988 | Taking advantage of optimal on-chip parallelism for parallel discrete-event simulation. Jack V. Briner Jr., John L. Ellis, Gershon Kedem |
| 1988 | Technology mapping for standard-cell generators. Michel R. C. M. Berkelaar, Jochen A. G. Jess |
| 1988 | Temperature measurement of simulated annealing placements. Jonathan Rose, Wolfgang Klebsch, Jürgen Wolf |
| 1988 | Test generation for sequential circuits using individual initial value propagation. Takuji Ogihara, Shuichi Saruyama, Shinichi Murai |
| 1988 | Testing oriented analysis of CMOS ICs with opens. Wojciech Maly, Pranab K. Nag, Phil Nigh |
| 1988 | The logic automation approach to accurate and efficient gate and functional level simulation. Michel Heydemann, Daniel Dure |
| 1988 | The use of inverse layout trees for hierarchical design verification. Nils Hedenstierna, Kjell O. Jeppson |
| 1988 | Time domain current waveform simulation of CMOS circuits. An-Chang Deng, Yan-Chyuan Shiau, K.-H. Loh |
| 1988 | Timing optimization of combinational logic. Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1988 | Topological channel routing. Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell |
| 1988 | Two-layer quad trees: a data structure for high-speed interactive layout tools. Wanhao Li, Scott Legendre, Kevin Gardiner |
| 1988 | Vectorized fault simulation on the Cray X-MP supercomputer. Füsun Özgüner, Raja Daoud |
| 1988 | XPSim: a MOS VLSI simulator. Romy L. Bauer, Jiayuan Fang, Antony P.-C. Ng, Robert K. Brayton |
| 1988 | iCOACH: a circuit optimization aid for CMOS high-performance circuits. H. Y. Chen, Sung-Mo Kang |
| 1988 | iEDISON: an interactive statistical design tool for MOS VLSI circuits. Tat-Kwan Yu, Sung-Mo Kang, Ibrahim N. Hajj, Timothy N. Trick |
| 1988 | iPRIDE: a parallel integrated circuit simulator using direct method. Mi-Chang Chang, Ibrahim N. Hajj |