HPCA A*

36 papers

YearTitle / Authors
200511th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA
2005A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks.
José Duato, Ian Johnson, José Flich, Finbar Naven, Pedro Javier García, Teresa Nachiondo Frinós
2005A Performance Comparison of DRAM Memory System Optimizations for SMT Processors.
Zhichun Zhu, Zhao Zhang
2005A Small, Fast and Low-Power Register File by Bit-Partitioning.
Masaaki Kondo, Hiroshi Nakamura
2005A Unified Compressed Memory Hierarchy.
Erik G. Hallnor, Steven K. Reinhardt
2005Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses.
Krishnan Sundaresan, Nihar R. Mahapatra
2005An Efficient Programmable 10 Gigabit Ethernet Network Interface Card.
Paul Willmann, Hyong-youb Kim, Scott Rixner, Vijay S. Pai
2005Characterizing and Comparing Prevailing Simulation Techniques.
Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag, David J. Lilja, Douglas M. Hawkins
2005Checkpointed Early Load Retirement.
Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez
2005Chip Multithreading: Opportunities and Challenges.
Lawrence Spracklen, Santosh G. Abraham
2005Distributing the Frontend for Temperature Reduction.
Pedro Chaparro, Grigorios Magklis, José González, Antonio González
2005Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications.
Lawrence Spracklen, Yuan Chou, Santosh G. Abraham
2005Enterprise IT Trends and Implications for Architecture Research.
Parthasarathy Ranganathan, Norman P. Jouppi
2005Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems.
Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai Huang, Paul R. Prucnal
2005Heat Stroke: Power-Density-Based Denial of Service in SMT.
Jahangir Hasan, Ankit Jalote, T. N. Vijaykumar, Carla E. Brodley
2005Improving Multiple-CMP Systems Using Token Coherence.
Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, David A. Wood
2005Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE.
Marc L. Corliss, E. Christopher Lewis, Amir Roth
2005Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.
Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy
2005Multithreaded Value Prediction.
Nathan Tuck, Dean M. Tullsen
2005On the Limits of Leakage Power Reduction in Caches.
Yan Meng, Timothy Sherwood, Ryan Kastner
2005Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.
Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron
2005Power Efficient Processor Architecture and The Cell Processor.
H. Peter Hofstee
2005Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture.
Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin
2005SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors.
Youtao Zhang, Lan Gao, Jun Yang, Xiangyu Zhang, Rajiv Gupta
2005SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs.
Feng Qin, Shan Lu, Yuanyuan Zhou
2005Scatter-Add in Data Parallel Architectures.
Jung Ho Ahn, Mattan Erez, William J. Dally
2005Software Directed Issue Queue Power Reduction.
Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González
2005Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.
Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
2005Tapping ZettaRAM
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg
2005The Future of Computer Architecture Research: An Industrial Perspective.
Wen-mei W. Hwu, Sanjay J. Patel
2005The Soft Error Problem: An Architectural Perspective.
Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt
2005Transition Phase Classification and Prediction.
Jeremy Lau, Stefan Schoenmackers, Brad Calder
2005Trends in High-Performance Processors.
Fred Weber
2005Unbounded Transactional Memory.
C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie
2005Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions.
Aamer Jaleel, Bruce L. Jacob
2005Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors.
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark