HPCA A*

43 papers

YearTitle / Authors
1999A Performance Comparison of Homeless and Home-Based Lazy Release Consistency Protocols in Software Shared Memory.
Alan L. Cox, Eyal de Lara, Y. Charlie Hu, Willy Zwaenepoel
1999A Scalable Cache Coherent Scheme Exploiting Wormhole Routing Networks.
Yunseok Rhee, Joonwon Lee
1999A Study of Control Independence in Superscalar Processors.
Eric Rotenberg, Quinn Jacobson, James E. Smith
1999Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory.
Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf
1999Communication Studies of Single-Threaded and Multithreaded Distributed-Memory Multiprocessors.
Andrew Sohn, Yunheung Paek, Jui-Yuan Ku, Yuetsu Kodama, Yoshinori Yamaguchi
1999Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory.
Sandhya Dwarkadas, Kourosh Gharachorloo, Leonidas I. Kontothanassis, Daniel J. Scales, Michael L. Scott, Robert Stets
1999Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors.
Maged M. Michael, Ashwini K. Nanda
1999Distributed Modulo Scheduling.
Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham
1999Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance.
David M. Brooks, Margaret Martonosi
1999Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs.
Koji Inoue, Koji Kai, Kazuaki J. Murakami
1999Efficient All-to-All Broadcast in All-Port Mesh and Torus Networks.
Yuanyuan Yang, Jianchao Wang
1999Exploiting Basic Block Value Locality with Block Reuse.
Jian Huang, David J. Lilja
1999Fifth Annual Workshop on Computer Education.
David R. Kaeli, Bruce L. Jacob
1999Global Context-Based Value Prediction.
Tarun Nakra, Rajiv Gupta, Mary Lou Soffa
1999Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors.
Ye Zhang, Lawrence Rauchwerger, Josep Torrellas
1999Impact of Buffer Size on the Efficiency of Deadlock Detection.
Juan-Miguel Martínez, Pedro López, José Duato
1999Improving CC-NUMA Performance Using Instruction-Based Prediction.
Stefanos Kaxiras, James R. Goodman
1999Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors.
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
1999Impulse: Building a Smarter Memory Controller.
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael A. Parker, Lambert Schaelicke, Terry Tateyama
1999Instruction Pre-Processing in Trace Processors.
Quinn Jacobson, James E. Smith
1999Instruction Recycling on a Multiple-Path Processor.
Steven Wallace, Dean M. Tullsen, Brad Calder
1999LAPSES: A Recipe for High Performance Adaptive Router Design.
Aniruddha S. Vaidya, Anand Sivasubramaniam, Chita R. Das
1999Lightweight Hardware Distributed Shared Memory Supported by Generalized Combining.
Kiyofumi Tanaka, Takashi Matsumoto, Kei Hiraki
1999Limits to the Performance of Software Shared Memory: A Layered Approach.
Angelos Bilas, Dongming Jiang, Yuanyuan Zhou, Jaswinder Pal Singh
1999MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs.
José Duato, Sudhakar Yalamanchili, María Blanca Caminero, Damon S. Love, Francisco J. Quiles
1999MP-LOCKs: Replacing H/W Synchronization Primitives with Message Passing.
Chen-Chi Kuo, John B. Carter, Ravindra Kuramkote
1999Memory Hierarchy Considerations for Fast Transpose and Bit-Reversals.
Kang Su Gatlin, Larry Carter
1999Multithreaded Execution Architecture and Compilation.
Dean M. Tullsen, Guang R. Gao
1999Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading.
Sébastien Hily, André Seznec
1999Parallel Computing for Irregular Applications.
Jacques Chassin de Kergommeaux, Yves Denneulin, Thierry Gautier
1999Parallel Dispatch Queue: A Queue-Based Programming Abstraction to Parallelize Fine-Grain Communication Protocols.
Babak Falsafi, David A. Wood
1999Permutation Development Data Layout (PDDL).
Thomas J. E. Schwarz, Jesse Steinberg, Walter A. Burkhard
1999Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999
1999RAPID-Cache - A Reliable and Inexpensive Write Cache for Disk I/O Systems.
Yiming Hu, Qing Yang, Tycho Nightingale
1999Second Workshop on Computer Architecture Evaluation Using Commercial Workloads.
Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas
1999Sensitivity of Parallel Applications to Large Differences in Bandwidth and Latency in Two-Layer Interconnects.
Aske Plaat, Henri E. Bal, Rutger F. H. Hofman
1999Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor.
Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy
1999Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors.
Ravi R. Iyer, Laxmi N. Bhuyan
1999The Impact of Link Arbitration on Switch Performance.
Marius Pirvu, Laxmi N. Bhuyan, Nan Ni
1999The Synergy of Multithreading and Access/Execute Decoupling.
Joan-Manuel Parcerisa, Antonio González
1999Third Workshop on Communication, Architecture, and Applications for Network-Based Parallel Computing (CANPC '99).
Anand Sivasubramaniam, Mario Lauria
1999Using Lamport Clocks to Reason about Relaxed Memory Models.
Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin
1999WildFire: A Scalable Path for SMPs.
Erik Hagersten, Michael Koster