| 2025 | 35th International Conference on Field-Programmable Logic and Applications, FPL 2025, Leiden, The Netherlands, September 1-5, 2025 |
| 2025 | A High-Performance and Resource-Efficient FPGA-Based Multi-Object Tracking System Using Event Cameras. Wei Xiong, Jianfan Zhang, Xingzhe Zhu, Jiacheng Cao, Jian Wang, Jinmei Lai |
| 2025 | AMD Versal Implementations of FAM and SSCA Estimators. Carol Jingyi Li, Ruilin Wu, Philip H. W. Leong |
| 2025 | ATAPP: Architecture and Technology Aware Power Predictor for Unseen FPGAS. Zhigang Wei, Aman Arora, Emily Shriver, Lizy K. John |
| 2025 | Accelerating K-Means: A Vectorized Approach for AI Engines & Neural Processing Units. Eleonora Cabai, Giuseppe Sorrentino, Marco Domenico Santambrogio, Davide Conficconi |
| 2025 | Accelerating Transposed Convolutions on FPGA-Based Edge Devices. Jude Haris, José Cano |
| 2025 | AffiNiTy: A Multi-Scalar Multiplication Accelerator with a Novel Batched Inversion Architecture. Tong Wu, Niall Emmart, Oliver Diessel |
| 2025 | Analytical Buffer Sizing for Neural Network Inference Applications on FPGAs. Lukas Stasytis, Felix Jentzsch, Zsolt István |
| 2025 | Aspo: Constraint-Aware Bayesian Optimization for Fpga-Based Soft Processors. Haoran Wu, Ce Guo, Wayne Luk, Robert Mullins |
| 2025 | Cocotb-Pynq: Co-Simulating Python+RTL Applications Targeting Pynq Platforms with Cocotb. Gavin Lusby, Nachiket Kapre |
| 2025 | Compile in Seconds and Run on an FPGA with DynaRapid. Andrea Guerrieri, Isaac John Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne |
| 2025 | Connection Tracking at 400 Gbps. David Vodák, Oliver Gurka, Jirí Matousek, Daniel Kondys |
| 2025 | DEFA: Design Space Exploration for FPGA Overlay Accelerators Through Frequency Prediction and Bayesian Optimization. Qilong Zhu, Yunfei Dai, Shiyan Bi, Huizhen Kuang, Dylan Wang, Wenbo Yin, Lingli Wang |
| 2025 | DMA Calypte: Open-Source Ultra-Low Latency DMA Engine for FPGAs. Vladislav Válek, Martin Spinler, Jakub Cabal, Tomás Martínek |
| 2025 | Design Space Exploration of Fast RISC-V Processors for Scalable Kilo-Core FPGA Systems. Riadh Ben Abdelhamid, Vladislav Válek, Kevin Klein, Dirk Koch |
| 2025 | Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah |
| 2025 | EQViTA: an End-To-End Quantized Vision Transformer Accelerator Implemented on Resource-Constrained FPGAs. Jiacheng Cao, Jiaqi Guo, Wei Xiong, Huanlin Luo, Jian Wang, Jinmei Lai |
| 2025 | EViL: An Efficient Vision-LSTM Accelerator Based on FPGA. Zexuan Deng, Han Jiao, Wenjin Huang, Yihua Huang |
| 2025 | Energy-Efficient DNNs on FPGAs for Edge-Cloud Computer Vision. Qaisar Farooq, Idilio Drago |
| 2025 | F Muhammad Shakeel Akram, Bogaraju Sharatchandra Varma, Vincent Meyers, Mehdi B. Tahoori, Dewar Finlay |
| 2025 | FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption. Zhihan Xu, Rajgopal Kannan, Viktor K. Prasanna |
| 2025 | FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMS. Shashwat Khandelwal, Jakoba Petri-Koenig, Thomas B. Preußer, Michaela Blott, Shanker Shreejith |
| 2025 | FLAIC: A Novel FPGA Logic Architecture via Fine-Grained Cut Topology Analysis. Xianfeng Cao, Huizhen Kuang, Yuanqi Wang, Lingli Wang |
| 2025 | FPGA Stereo Visual Slam with Efficient Stereo Feature Matching and Key-Frame Generation. Miyuru Thathsara, Damith Anhettigama, Siew-Kei Lam |
| 2025 | FPGA-Based MPSoCs for High-Performance Sensor Fusion: Accelerating Covariance Intersection. Hazem M. Sharf, Mohamed Hassan |
| 2025 | FPGAs with FABulous - Framework and Chips. Dirk Koch, Myrtle Shah, King Lok Chung, Jonas Kuenstler, Marcel Jung, Jakob Ternes, Asma Mohsin, Gennadiy Knis |
| 2025 | Four-Input Lookup Table (LUT4) and Architectural Enhancements Enable Power Efficient Mid-Range FPGAs. Satwant Singh, Michael Schneider, Ziad Aboud, Jonathan Peterson, Senani Gunaratna, Ting Yew, Cindy Lee, Rick Crotty |
| 2025 | From Errors to Solutions: LLM-Powered Command Scripting for FPGA Cad Tools. Mohamed A. Elgammal, Vaughn Betz |
| 2025 | GAMA: High-Performance GEMM Acceleration on AMD Versal ML-Optimized AI Engines. Kaustubh Manohar Mhatre, Endri Taka, Aman Arora |
| 2025 | GEF: A GNN-Based Evaluation Framework for FPGA Routing Architecture. Yuanqi Wang, Yunfei Dai, Jiangnan Li, Kaixiang Zhu, Huizhen Kuang, Hao Zhou, Eric Ren, Xifan Tang, Weijun Qin, Tao Li, Lingli Wang |
| 2025 | Hybrid Weightless Neural Networks for Efficient Edge Inference. Mugdha P. Jadhao, Alan T. L. Bacellar, Shashank Nag, Igor D. S. Miranda, Felipe M. G. França, Lizy K. John |
| 2025 | Identifying Sat Resilient Blocks Through LUT Switching Analysis for Breaking Compound Logic Locking Schemes. Binbin Wang, Xinmu Wang, Xinyu Zhang, Shibo Tang, Huisi Zhou, Wei Hu |
| 2025 | Improving Boolean Satisfiability-Based Modulo Scheduling. Nicolai Fiege, Peter Zipf |
| 2025 | Interconnection-Aware Resynthesis for Improving FPGA Physical Design. Xiaoke Wang, Dirk Stroobandt |
| 2025 | Live Demonstration: Continuous Processing of Event-Data with Graph Convolutional Neural Networks Implemented for SoC FPGA. Piotr Wzorek, Kamil Jeziorek, Marcin Kowalczyk, Krzysztof Blachut, Tomasz Kryjak, Marek Gorgon |
| 2025 | Maximizing Resource Utilization for Stencil Computing. Pedro Henrique Di Francia Rosso, Guido Araujo |
| 2025 | Maximum FPGA: A 32K-Point 32-Parallel Floating Point FFT. Martin Langhammer, Bogdan Pasca |
| 2025 | Multi-FPGA Programming Using OpenMP. Pedro Henrique Di Francia Rosso, Guido Araujo |
| 2025 | Multiplexer Optimizations for Virtex FPGAs. Nicolai Fiege, Martin Hardieck, Peter Zipf |
| 2025 | NPX: Automating Neuromorphic Processor Design from Spike-Based Learning to FPGA Prototyping. Kyuseung Han, Hyeonguk Jang, Sukho Lee, Sung-Eun Kim, Kyudong Hwang, Jae-Jin Lee |
| 2025 | NeuGEMM: A Reordering-Free Unified GEMM-Conv2D Accelerator for Lightweight Neuromorphic Processors. Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han |
| 2025 | Open-Source FPGA Routing Runtime Prediction for Improved Productivity Via Smart Route Termination. Andrew David Gunter, Steven J. E. Wilton |
| 2025 | Performance Impact on Reducing Energy Consumption Applying Adaptive Stream-Based Entropy Coding on FPGA. Taku Nishikawa, Koichi Marumo, Shinichi Yamagiwa |
| 2025 | Programmable Congestion Generator for Evaluating FPGA Interconnect Robustness. Atreyee Saha, Sandesh Goyal, Aashish Tripathi |
| 2025 | ReconFormer: A Multi-Level Run-Time Reconfigurable System-on-Chip for Accelerating Transformers. Je Yang, Gabriele Tombesi, Joseph Zuckerman, Luca P. Carloni |
| 2025 | Reducing FPGA Placement Runtime by Clustering of Netlist Blocks. Markus Rein, Dirk Stroobandt |
| 2025 | Refining Datapath for Microscaling ViTs. Can Xiao, Jianyi Cheng, Yiren Zhao |
| 2025 | Routing Struggle: A Metric to Quantify Routability. Sadegh Yazdanshenas, Jeffrey Chromczak |
| 2025 | Routino: Accelerating FPGA Routing Through Efficient Memory Representation. Davide Nicolini, Corrado De Sio, Eleonora Vacca, Luca Sterpone |
| 2025 | SparseDPD: A Sparse Neural Network-Based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization. Manno Versluis, Yizhuo Wu, Chang Gao |
| 2025 | TRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro Placer. Qin Luo, Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong |
| 2025 | Towards Accelerated Healthcare Federated System Through Heterogeneous Accelerators. Giuseppe Sorrentino, Davide Conficconi |
| 2025 | Towards Instruction-Controlled In-Pipeline GEMM Acceleration in a Dual-Issue RISC-V Core for Edge Applications. Ahmad Othman, Darmen Ilyas, Ahmed Kamaleldin, Diana Göhringer |
| 2025 | URAM-Based Asynchronous FIFO Design for Improved Throughput and FPGA RAM Usage. Martim Rosado, Pedro Tomás, Nuno Roma, André David |
| 2025 | Using Data to Reduce Uncertainty in FPGA Routing. Andrew David Gunter, Steven J. E. Wilton |
| 2025 | Versatile Place and Route with Continuous Routing Runtime Prediction and Smart Route Termination. Andrew David Gunter, Steven J. E. Wilton |
| 2025 | Virtualization and Dynamic Reconfiguration of Custom Instruction Accelerators (CIA) in RISC-V Embedded Systems. Bea Healy, Brandon Freiberger, Jonas Kuenstler, King Lok Chung, Emil Cozac, Meinhard Kissich, Gennadiy Knis, Ron Sass, Dirk Koch, Jan Gray, Guy Lemieux |