| 2020 | 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020 Nele Mentens, Leonel Sousa, Pedro Trancoso, Miquel Pericàs, Ioannis Sourdis |
| 2020 | A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS. Ryusuke Nebashi, Naoki Banno, Makoto Miyamura, Xu Bai, Kazunori Funahashi, Koichiro Okamoto, Noriyuki Iguchi, Hideaki Numata, Tadahiko Sugibayashi, Toshitsugu Sakamoto, Munehiro Tada |
| 2020 | A Configurable TLB Hierarchy for the RISC-V Architecture. Nikolaos Charalampos Papadopoulos, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Dionisios N. Pnevmatikatos |
| 2020 | A Deep-Learning Framework for Predicting Congestion During FPGA Placement. Dani Maarouf, Ahmed Shamli, Timothy Martin, Gary Gréwal, Shawki Areibi |
| 2020 | A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs. Richard Dorrance, Andrey Belogolovy, Hechen Wang, Xue Zhang |
| 2020 | A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde |
| 2020 | A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGA. Abbas Haghi, Lluc Alvarez, Jordà Polo, Dionysios Diamantopoulos, Christoph Hagleitner, Miquel Moretó |
| 2020 | A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution. Justin Knapheide, Benno Stabernack, Maximilian Kuhnke |
| 2020 | A High-Performance Out-of-Order Soft Processor Without Register Renaming. Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai |
| 2020 | A Seamless DFT/FFT Self-Adaptive Architecture for Embedded Radar Applications. Julien Mazuet, Michel Narozny, Catherine Dezan, Jean-Philippe Diguet |
| 2020 | A Self-Compilation Flow Demo on FOS - The FPGA Operating System. Khoa Dang Pham, Anuj Vaishnav, Joseph Powell, Dirk Koch |
| 2020 | A Service-Oriented Memory Architecture for FPGA Computing. Joseph Melber, James C. Hoe |
| 2020 | A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern. Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, Li Jiang |
| 2020 | Accelerating Local Laplacian Filters on FPGAs. Shashwat Khandelwal, Ziaul Choudhury, Shashwat Shrivastava, Suresh Purini |
| 2020 | Acceleration of Simulation Models Through Automatic Conversion to FPGA Hardware. Frans Skarman, Oscar Gustafsson, Daniel Jung, Mattias Krysander |
| 2020 | Agile Autotuning of a Transprecision Tensor Accelerator Overlay for TVM Compiler Stack. Dionysios Diamantopoulos, Burkhard Ringlein, Mitra Purandare, Gagandeep Singh, Christoph Hagleitner |
| 2020 | An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics. Philippos Papaphilippou, Chris Brooks, Wayne Luk |
| 2020 | An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks. Ryosuke Kuramochi, Hiroki Nakahara |
| 2020 | Automated Design of FPGAs Facilitated by Cycle-Free Routing. Ang Li, Ting-Jung Chang, David Wentzlaff |
| 2020 | Caffe Barista: Brewing Caffe with FPGAs in the Training Loop. Diederik Adriaan Vink, Aditya Rajagopal, Stylianos I. Venieris, Christos-Savvas Bouganis |
| 2020 | Characterizing Latency Overheads in the Deployment of FPGA Accelerators. Ryan A. Cooke, Suhaib A. Fahmy |
| 2020 | Compact and Programmable yet High-Performance SoC Architecture for Cryptographic Pairings. Milad Bahadori, Kimmo Järvinen |
| 2020 | Demo: A Closer Look at Malicious Bitstreams. Tuan La, Kaspar Matas, Joseph Powell, Khoa Dang Pham, Dirk Koch |
| 2020 | Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-Efficiency. Erhan Baturay Onural, Ismail Emir Yuksel, Behzad Salami |
| 2020 | Design for ReConfigurability: An Electronic System Level Methodology to Exploit Reconfigurable Platforms. Gabriella D'Andrea, Luigi Pomante |
| 2020 | Dynamically Growing Neural Network Architecture for Lifelong Deep Learning on the Edge. Duvindu Piyasena, Miyuru Thathsara, Sathursan Kanagarajah, Siew Kei Lam, Meiqing Wu |
| 2020 | Efficient Ab-Initio Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGAs. Arjun Ramaswami, Tobias Kenter, Thomas D. Kühne, Christian Plessl |
| 2020 | Endurance-Aware RRAM-Based Reconfigurable Architecture using TCAM Arrays. João Paulo Cardoso de Lima, Marcelo Brandalero, Luigi Carro |
| 2020 | Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. Nuno Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso |
| 2020 | Exploring FPGA Optimizations in OpenCL for Breadth-First Search on Sparse Graph Datasets. Atharva Gondhalekar, Wu-chun Feng |
| 2020 | FLASH: FPGA Locality-Aware Sensitive Hash for Nearest Neighbor Search and Clustering Application. Wei Yan, Fatemeh Tehranipoor, Xuan Zhang, John A. Chandy |
| 2020 | FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen |
| 2020 | FPGA Acceleration of Ray-Based Iterative Algorithm for 3D Low-Dose CT Reconstruction. Linjun Qiao, Guojie Luo, Wentai Zhang, Ming Jiang |
| 2020 | FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation. Shashwat Shrivastava, Ziaul Choudhury, Shashwat Khandelwal, Suresh Purini |
| 2020 | Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation. Yanqi Liu, Giuseppe Calderoni, Ruth Iris Bahar |
| 2020 | High Bandwidth Memory on FPGAs: A Data Analytics Perspective. Kaan Kara, Christoph Hagleitner, Dionysios Diamantopoulos, Dimitris Syrivelis, Gustavo Alonso |
| 2020 | High-Speed Chromatic Dispersion Compensation Filtering in FPGAs for Coherent Optical Communication. Cheolyong Bae, Oscar Gustafsson |
| 2020 | HyperLogLog Sketch Acceleration on FPGA. Amit Kulkarni, Monica Chiosa, Thomas B. Preußer, Kaan Kara, David Sidler, Gustavo Alonso |
| 2020 | LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs. Farah Abid, Darshana Jayasinghe, Sompasong Somsavaddy, Sri Parameswaran |
| 2020 | Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers. Gurshaant Malik, Ian Elmor Lang, Rodolfo Pellizzoni, Nachiket Kapre |
| 2020 | Lightweight Side-Channel Protection using Dynamic Clock Randomization. Benjamin Hettwer, Kallyan Das, Sebastien Leger, Stefan Gehrer, Tim Güneysu |
| 2020 | LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications. Yaman Umuroglu, Yash Akhauri, Nicholas James Fraser, Michaela Blott |
| 2020 | MCEA: A Resource-Aware Multicore CGRA Architecture for the Edge. Guilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Michael Hübner, Mateus Beck Rutzig, Antonio Carlos Schneider Beck |
| 2020 | Mask Scrambling Against SCA on Reconfigurable TBOX-Based AES. João Carlos Resende, Ricardo J. R. Maçãs, Ricardo Chaves |
| 2020 | Measuring the Accuracy of Layout Area Estimation Models of Tile-Based FPGAs in FinFET Technology. Sajjad Rostami Sani, Farheen Fatima Khan, Anas Razzaq, Andy Gean Ye |
| 2020 | NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling. Gagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Juan Gómez-Luna, Sander Stuijk, Onur Mutlu, Henk Corporaal |
| 2020 | On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs. Naoki Fujieda |
| 2020 | Partial Reconfiguration for Design Optimization. Marie Nguyen, Nathan Serafin, James C. Hoe |
| 2020 | Power Wasting Circuits for Cloud FPGA Attacks. George Provelengios, Daniel E. Holcomb, Russell Tessier |
| 2020 | Precise Pointer Analysis in High-Level Synthesis. Nadesh Ramanathan, George A. Constantinides, John Wickerson |
| 2020 | RANTT: A RISC-V Architecture Extension for the Number Theoretic Transform. Emre Karabulut, Aydin Aysu |
| 2020 | RISC-V FPGA Platform Toward ROS-Based Robotics Application. Jaewon Lee, Hanning Chen, Jeffrey S. Young, Hyesoon Kim |
| 2020 | RapidLayout: Fast Hard Block Placement of FPGA-Optimized Systolic Arrays using Evolutionary Algorithms. Niansong Zhang, Xiang Chen, Nachiket Kapre |
| 2020 | Resource Elastic Database Acceleration. Kristiyan Manev, Dirk Koch |
| 2020 | Secret Sharing MPC on FPGAs in the Datacenter. Pierre-Francois Wolfe, Rushi Patel, Robert Munafo, Mayank Varia, Martin C. Herbordt |
| 2020 | Securing FPGA Accelerators at the Electrical Level for Multi-tenant Platforms. Tuan La, Kaspar Matas, Khoa Dang Pham, Dirk Koch |
| 2020 | Side Channel Resistance at a Cost: A Comparison of ARX-Based Authenticated Encryption. Flora Coleman, Behnaz Rezvani, Sachin Sachin, William Diehl |
| 2020 | Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs. Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton |
| 2020 | TTA-SIMD Soft Core Processors. Kati Tervo, Samawat Malik, Topi Leppänen, Pekka Jääskeläinen |
| 2020 | Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. Stefan Nikolic, Grace Zgheib, Paolo Ienne |
| 2020 | Transparent Integration of a Dynamic FPGA Database Acceleration System. Kaspar Mätas, Dirk Koch |
| 2020 | Using DSP Slices as Content-Addressable Update Queues. Thomas B. Preußer, Monica Chiosa, Alexander Weiss, Gustavo Alonso |
| 2020 | Using Novel Configuration Techniques for Accelerated FPGA Aging. Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings |
| 2020 | Weighing Up the New Kid on the Block: Impressions of using Vitis for HPC Software Development. Nick Brown |
| 2020 | X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs. Dina G. Mahmoud, Wei Hu, Mirjana Stojilovic |