| 2017 | "All programmable FPGA, providing hardware efficiency to software programmers". Ivo Bolsens |
| 2017 | 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, September 4-8, 2017 Marco D. Santambrogio, Diana Göhringer, Dirk Stroobandt, Nele Mentens, Jari Nurmi |
| 2017 | A demonstration of the GUINNESS: A GUI based neural NEtwork SyntheSizer for an FPGA. Hiroyuki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Simpei Sato |
| 2017 | A dynamic partial reconfigurable overlay concept for PYNQ. Benedikt Janßen, Pascal Zimprich, Michael Hübner |
| 2017 | A fair and comprehensive large-scale analysis of oscillation-based PUFs for FPGAs. Alexander Wild, Georg T. Becker, Tim Güneysu |
| 2017 | A fully connected layer elimination for a binarizec convolutional neural network on an FPGA. Hiroki Nakahara, Tomoya Fujii, Shimpei Sato |
| 2017 | A generic high throughput architecture for stream processing. Christos Rousopoulos, Ektoras Karandeinos, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos |
| 2017 | A high-performance system-on-chip architecture for direct tracking for SLAM. Konstantinos Boikos, Christos-Savvas Bouganis |
| 2017 | A high-throughput reconfigurable processing array for neural networks. Ephrem Wu, Xiaoqian Zhang, David Berman, Inkeun Cho |
| 2017 | A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN. Robin Aggleton, Luis E. Ardila-Perez, Fionn Amhairghen Ball, Matthias Norbert Balzer, James John Brooke, Luigi Calligaris, Michele Caselle, Davide Cieri, Emyr John Clement, Geoffrey Hall, Kristian Harder, Peter R. Hobson, Gregory M. Iles, Thomas James, Konstantinos Manolopoulos, Takashi Matsushita, Alexander D. Morton, David Newbold, Sudarshan Paramesvaran, Mark Franco Pesaresi, Ivan D. Reid, Andrew W. Rose, Oliver Sander, Thomas Schuh, Claire Shepherd-Themistocleous, Antoni Shtipliyski, Sioni Paris Summers, Alexander D. Tapper, Ian Tomalin, Kirika Uchida, Paschalis Vichoudis, Marc Weber |
| 2017 | A partial reconfiguration based microphone array network emulator. Bruno da Silva, Federico Domínguez, An Braeken, Abdellah Touhafi |
| 2017 | A programming model and runtime system for approximation-aware heterogeneous computing. Ioannis Parnassos, Nikolaos Bellas, Nikolaos Katsaros, Nikolaos Patsiatzis, Athanasios Gkaras, Konstantinos Kanellis, Christos D. Antonopoulos, Michalis Spyrou, Manolis Maroudas |
| 2017 | A pythonic approach for rapid hardware prototyping and instrumentation. John Clow, Georgios Tzimpragos, Deeksha Dangwal, Sammy Guo, Joseph McMahan, Timothy Sherwood |
| 2017 | A security library for FPGA interlays. Anuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch |
| 2017 | A systematic approach to design and optimise streaming applications on FPGA using high-level synthesis. Mohammad Hosseinabady, José Luis Núñez-Yáñez |
| 2017 | ARMHEx: A framework for efficient DIFT in real-world SoCs. Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat |
| 2017 | ARMHEx: A hardware extension for DIFT on ARM-based SoCs. Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat |
| 2017 | Accelerated analysis of Boolean gene regulatory networks. Mitra Purandare, Raphael Polig, Christoph Hagleitner |
| 2017 | Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton |
| 2017 | Accelerating low bit-width convolutional neural networks with embedded FPGA. Li Jiao, Cheng Luo, Wei Cao, Xuegong Zhou, Lingli Wang |
| 2017 | Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA. Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano |
| 2017 | An FPGA hardware implementation approach for a phylogenetic tree reconstruction algorithm with incremental tree optimization. Henry Block, Tsutomu Maruyama |
| 2017 | An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo |
| 2017 | An implementation method of poisson image editing on FPGA. Ryouhei Maeda, Tsutomu Maruyama |
| 2017 | An implementation of list successive cancellation decoder with large list size for polar codes. ChenYang Xia, YouZhe Fan, Ji Chen, Chi-Ying Tsui, Chongyang Zeng, Jie Jin, Bin Li |
| 2017 | Application-specific soft-core vector processor for advanced driver assistance systems. Stephan Nolting, Florian Giesemann, Julian Hartig, Achim Schmider, Guillermo Payá-Vayá |
| 2017 | Area-optimized montgomery multiplication on IGLOO 2 FPGAs. Pedro Maat C. Massolino, Lejla Batina, Ricardo Chaves, Nele Mentens |
| 2017 | Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch |
| 2017 | Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software. Yu Ting Chen, Jason Helge Anderson |
| 2017 | Body bias optimization for variable pipelined CGRA. Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano |
| 2017 | Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. Yohann Uguen, Florent de Dinechin, Steven Derrien |
| 2017 | Broken-Karatsuba multiplication and its application to Montgomery modular multiplication. Jinnan Ding, Shuguo Li |
| 2017 | Comparison of hardware and software implementations of selected lightweight block ciphers. William Diehl, Farnoud Farahmand, Panasayya Yalla, Jens-Peter Kaps, Kris Gaj |
| 2017 | Complete activation scheme for FPGA-oriented IP cores design protection. Brice Colombier, Ugo Mureddu, Marek Laban, Oto Petura, Lilian Bossuet, Viktor Fischer |
| 2017 | Customised pearlmutter propagation: A hardware architecture for trust region policy optimisation. Shengjia Shao, Wayne Luk |
| 2017 | DFiant: A dataflow hardware description language. Oron Port, Yoav Etsion |
| 2017 | Decision tree based hardware power monitoring for run time dynamic power management in FPGA. Zhe Lin, Wei Zhang, Sharad Sinha |
| 2017 | Deflection-routed butterfly fat trees on FPGAs. Nachiket Kapre |
| 2017 | Demonstration of a partial reconfiguration based microphone array network emulator. Bruno da Silva, Federico Domínguez, An Braeken, Abdellah Touhafi |
| 2017 | Deploying FPGAs to future-proof genome-wide analyses based on linkage disequilibrium. Dimitrios Bozikas, Nikolaos Alachiotis, Pavlos Pavlidis, Euripides Sotiriades, Apostolos Dollas |
| 2017 | Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final addition. Jinnan Ding, Shuguo Li |
| 2017 | Dynamic bitwidth assignment for efficient dot products. Simon Joel Schmidt, David Boland |
| 2017 | Dynamic power estimation based on switching activity propagation. Yehya Nasser, Jean-Christophe Prévotet, M. Heiard, Jordane Lorandel |
| 2017 | Enabling partial reconfiguration and low latency routing using segmented FPGA NoCs. Kizheppatt Vipin, Jan Gray, Nachiket Kapre |
| 2017 | Evaluating FPGA clusters under wide ranges of design parameters. Grace Zgheib, Paolo Ienne |
| 2017 | Evaluating high-level design strategies on FPGAs for high-performance computing. Artur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka |
| 2017 | Evaluating high-level design strategies on FPGAs for high-performance computing. Artur Podobas, Hamid Reza Zohouri, Naoya Maruyama, Satoshi Matsuoka |
| 2017 | Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench. Yingyi Luo, Xianshan Wen, Kazutomo Yoshii, Seda Ogrenci Memik, Gokhan Memik, Hal Finkel, Franck Cappello |
| 2017 | Exploration of OpenCL for FPGAs using SDAccel and comparison to GPUs and multicore CPUs. Lester Kalms, Diana Göhringer |
| 2017 | Exploring the potential of reconfigurable platforms for order book update. Conghui He, Haohuan Fu, Wayne Luk, Weijia Li, Guangen Yang |
| 2017 | F-C3D: FPGA-based 3-dimensional convolutional neural network. Hongxiang Fan, Xinyu Niu, Qiang Liu, Wayne Luk |
| 2017 | FISH: Linux system calls for FPGA accelerators. Kevin Nam, Blair Fort, Stephen Brown |
| 2017 | FPGA acceleration of multilevel ORB feature extraction for computer vision. Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond |
| 2017 | FPGA acceleration of spark applications in a Pynq cluster. Christoforos Kachris, Elias Koromilas, Ioannis Stamelos, Dimitrios Soudris |
| 2017 | FPGA acceleration of the scoring process of X!TANDEM for protein identification. Jin Qiu, Ping Kang, Li Ding, Yipeng Yuan, Wenbo Yin, Lingli Wang |
| 2017 | FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai |
| 2017 | FPGA modeling techniques for detecting and demodulating multiple wireless protocols. Benjamin Drozdenko, Suranga Handagala, Kaushik R. Chowdhury, Miriam Leeser |
| 2017 | FPGA-based design of a self-checking TMR voter. Umar Afzaal, Jeong-A Lee |
| 2017 | Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairs. Yifeng Mo, Shuguo Li |
| 2017 | Find the real speed limit: FPGA CAD for chip-specific application delay measurement. Ibrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz |
| 2017 | Flexible FPGA design for FDTD using OpenCL. Tobias Kenter, Jens Förstner, Christian Plessl |
| 2017 | Functional & timing in-hardware verification of FPGA-based designs using unit testing frameworks. Julián Caba, Fernando Rincón, Julio Dondo Gazzano |
| 2017 | Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs. Thomas B. Preußer |
| 2017 | HPC on FPGA clouds: 3D FFTs and implications for molecular dynamics. Jiayi Sheng, Chen Yang, Ahmed Sanaullah, Michael Papamichael, Adrian M. Caulfield, Martin C. Herbordt |
| 2017 | Heterogeneous virtualized network function framework for the data center. Naif Tarafdar, Thomas Lin, Nariman Eskandari, David Lion, Alberto Leon-Garcia, Paul Chow |
| 2017 | High performance binary neural networks on the Xeon+FPGA™ platform. Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong |
| 2017 | High throughput AES encryption/decryption with efficient reordering and merging techniques. Lijuan Li, Shuguo Li |
| 2017 | High-performance video content recognition with long-term recurrent convolutional network for FPGA. Xiaofan Zhang, Xinheng Liu, Anand Ramachandran, Chuanhao Zhuge, Shibin Tang, Peng Ouyang, Zuofu Cheng, Kyle Rupnow, Deming Chen |
| 2017 | High-quality view interpolation based on depth maps and its hardware implementation. Yanzhe Li, Kai Huang, Luc Claesen |
| 2017 | In-network online data analytics with FPGAs. Ryan A. Cooke, Suhaib A. Fahmy |
| 2017 | In-switch approximate processing: Delayed tasks management for MapReduce applications. Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani |
| 2017 | K-means clustering on CGRA. João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias |
| 2017 | Kiwi scientific acceleration at large: Incremental compilation and multi-FPGA HLS demo. David J. Greaves |
| 2017 | Latency-driven design for FPGA-based convolutional neural networks. Stylianos I. Venieris, Christos-Savvas Bouganis |
| 2017 | Learning-based interconnect-aware dataflow accelerator optimization. Shuangnan Liu, Benjamin Carrión Schäfer |
| 2017 | Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators. Weina Lu, Wenyan Lu, Jing Ye, Yu Hu, Xiaowei Li |
| 2017 | Line rate programmable packet processing in 100Gb networks. Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely |
| 2017 | Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit. Jose Raul Garcia Ordaz, Dirk Koch |
| 2017 | Mapping of P4 match action tables to FPGA. Michal Kekely, Jan Korenek |
| 2017 | On accelerating pair-HMM computations in programmable hardware. Subho S. Banerjee, Mohamed El-Hadedy, Ching Y. Tan, Zbigniew T. Kalbarczyk, Steven S. Lumetta, Ravishankar K. Iyer |
| 2017 | One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs. Gaël Deest, Tomofumi Yuki, Sanjay V. Rajopadhye, Steven Derrien |
| 2017 | OpenSoC system architect: An open toolkit for building soft-cores on FPGAs. Farzad Fatollahi-Fard, David Donofrio, John Shalf, John D. Leidel, Xi Wang, Yong Chen |
| 2017 | Optimizing streaming stencil time-step designs via FPGA floorplanning. Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio |
| 2017 | PAAS: A system level simulator for heterogeneous computing architectures. Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang |
| 2017 | Parallel FPGA routing: Survey and challenges. Mirjana Stojilovic |
| 2017 | Parallel RRT∗ architecture design for motion planning. Size Xiao, Neil Bergmann, Adam Postula |
| 2017 | Parallel dot-products for deep learning on FPGA. Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto |
| 2017 | Phase calibrated ring oscillator PUF design and implementation on FPGAs. Wei Yan, Chenglu Jin, Fatemeh Tehranipoor, John A. Chandy |
| 2017 | PolyPC: Polymorphic parallel computing framework on embedded reconfigurable system. Hongyuan Ding, Miaoqing Huang |
| 2017 | Quantifying and mitigating the costs of FPGA virtualization. Sadegh Yazdanshenas, Vaughn Betz |
| 2017 | REAPR: Reconfigurable engine for automata processing. Ted Xie, Vinh Dang, Jack Wadden, Kevin Skadron, Mircea Stan |
| 2017 | Rapid implementation of a partially reconfigurable video system with PYNQ. Brad L. Hutchings, Michael J. Wirthlin |
| 2017 | Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts. Ho-Cheung Ng, Shuanglong Liu, Wayne Luk |
| 2017 | Reliable SEU monitoring and recovery using a programmable configuration controller. Lingkan Gong, Alexander Kroh, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel |
| 2017 | Relocation-aware communication network for circuits on Xilinx FPGAs. Adewale Adetomi, Godwin Enemali, Tughrul Arslan |
| 2017 | STRIPE: Signal selection for runtime power estimation. James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides |
| 2017 | Scalable high-performance architecture for convolutional ternary neural networks on FPGA. Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot, Hande Alemdar, Nicholas Caldwell, Vincent Leroy |
| 2017 | Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms. Muhsen Owaida, Hantian Zhang, Ce Zhang, Gustavo Alonso |
| 2017 | Shielding non-trusted IPs in SoCs. Festus Hategekimana, Taylor J. L. Whitaker, Md Jubaer Hossain Pantho, Christophe Bobda |
| 2017 | TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features. Eric Matthews, Lesley Shannon |
| 2017 | The Monte Carlo PUF. Vladimir Rozic, Bohan Yang, Jo Vliegen, Nele Mentens, Ingrid Verbauwhede |
| 2017 | Tile size selection for optimized memory reuse in high-level synthesis. Junyi Liu, John Wickerson, George A. Constantinides |
| 2017 | Toward a pixel-parallel architecture for graph cuts inference on FPGA. Tianqi Gao, Jungwook Choi, Shang-nien Tsai, Rob A. Rutenbar |
| 2017 | Transparent memory encryption and authentication. Mario Werner, Thomas Unterluggauer, Robert Schilling, David Schaffenrath, Stefan Mangard |
| 2017 | Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices. Stephan Nolting, Lin Liu, Guillermo Payá-Vayá |
| 2017 | Validating optimisations for chaotic simulations. James Stanley Targett, Peter D. Düben, Wayne Luk |
| 2017 | Versatile deployment of FPGA accelerators in disaggregated data centers: A bioinformatics case study. Nikolaos Alachiotis, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos |
| 2017 | VineTalk: Simplifying software access and sharing of FPGAs in datacenters. Stelios Mavridis, Emmanouil Pavlidakis, Ioannis Stamoulias, Christos Kozanitis, Nikolaos Chrysos, Christoforos Kachris, Dimitrios Soudris, Angelos Bilas |
| 2017 | Vivado design interface: An export/import capability for Vivado FPGA designs. Thomas Townsend, Brent E. Nelson |
| 2017 | Voltage drop-based fault attacks on FPGAs using valid bitstreams. Dennis R. E. Gnad, Fabian Oboril, Mehdi Baradaran Tahoori |
| 2017 | doppioDB: A hardware accelerated database. David Sidler, Muhsen Owaida, Zsolt István, Kaan Kara, Gustavo Alonso |