FPL B

112 papers

YearTitle / Authors
2010A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs.
Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch
2010A Compact Transactional Memory Multiprocessor System on FPGA.
Matteo Pusceddu, Simone Ceccolini, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo
2010A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core Processor.
Gerald Hempel, Christian Hochberger, Andreas Koch
2010A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs.
Marcus Ritt, Carlos Arthur Lang Lisbôa, Luigi Carro, Cristiano Lazzari
2010A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware Compilation.
Hagen Gädke-Lütjens, Benjamin Thielmann, Andreas Koch
2010A Karatsuba-Based Montgomery Multiplier.
Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip Heng Wai Leong
2010A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems.
Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada
2010A Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog Blocks.
Wen-Hui Fu, Jun Jiang, Xi Qin, Ting Yi, Zhiliang Hong
2010A Reconfigurable Computing Scheduler Optimized for Multicore Systems.
Philip Garcia, Kyle Rupnow, Katherine Compton
2010A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis.
Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon
2010A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching.
Francesco Bruschi, Marco Paolieri, Vincenzo Rana
2010A Scalable, High-Performance Motion Estimation Application for a Weakly-Programmable FPGA Architecture.
Henning Sahlbach, Sean Whitty, Oliver Bende, Rolf Ernst
2010A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.
Heiner Giefers, Marco Platzner
2010ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs.
Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster
2010Accurate Time-to-Digital Converter Based on Xilinx's Digital Clock Managers.
Ángel Quirós-Olozábal, Ma de los Ángeles Cifredo Chacón, José María Guerrero-Rodríguez
2010Advanced Multithreading Architecture with Hardware Based Scheduling.
Ye Lu, Sakir Sezer, John V. McCanny
2010An FPGA Based Hybrid Processor Emulation Platform.
Qigang Wang, Rolf Kassa, Wenbo Shen, Nelson Ijih, Bhushan Chitlur, Michael Konow, Dong Liu, Arthur Sheiman, Prabhat Gupta
2010An FPGA-based High-Speed, Low-Latency Processing System for High-Energy Physics.
Stefan Kirsch, Felix Rettig, Dirk Hutter, Jan de Cuveland, Venelin Angelov, Volker Lindenstruth
2010An FPGA-based Transverse Multibunch Feedback System for Diamond Light Source.
Isa Uzun, Mark Heron, Alun Morgan, Guenther Rehm
2010An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier.
Malte Baesler, Sven-Ole Voigt, Thomas Teufel
2010An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs.
Brian Leung, Chih-Hung Wu, Seda Ogrenci Memik, Sanjay Mehrotra
2010Automation Framework for Large-Scale Regular Expression Matching on FPGA.
Thilan Ganegedara, Yi-Hua E. Yang, Viktor K. Prasanna
2010Breaking Elliptic Curve Cryptosystems Using Reconfigurable Hardware.
Junfeng Fan, Daniel V. Bailey, Lejla Batina, Tim Güneysu, Christof Paar, Ingrid Verbauwhede
2010COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization.
Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2010Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC Core.
Fabio Garzia, Waqar Hussain, Jari Nurmi
2010Customized Exposed Datapath Soft-Core Design Flow with Compiler Support.
Otto Esko, Pekka Jääskeläinen, Pablo Huerta, Carlos S. de La Lama, Jarmo Takala, José Ignacio Martínez
2010Decision Forest: A Scalable Architecture for Flexible Flow Matching on FPGA.
Weirong Jiang, Viktor K. Prasanna, Norio Yamagaki
2010Degradation Analysis and Mitigation in FPGAs.
Edward A. Stott, Justin S. J. Wong, Peter Y. K. Cheung
2010Design and FPGA Implementation of a 2nd Order Adaptive Delta Sigma Modulator with One Bit Quantization.
Shahrukh Athar, Muhammad Ali Siddiqi, Shahid Masud
2010Design and Implementation of Real-Time Transactional Memory.
Martin Schoeberl, Peter Hilber
2010Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration.
Norbert Abel
2010Detecting Patterns in Various Size and Angle Using FPGA.
Masayuki Suzuki, Yoshifumi Tanida, Tsutomu Maruyama
2010Dynamic Reconfiguration Optimisation with Streaming Data Decompression.
Atukem Nabina, José L. Núñez-Yáñez
2010Dynamically Reconfigurable Vision-Chip Architecture.
Maki Yasuda, Minoru Watanabe
2010ERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable Computing.
Daniel W. Chang, Christipher D. Jenkins, Philip C. Garcia, Syed Zohaib Gilani, Paula Aguilera, Aishwarya Nagarajan, Michael J. Anderson, Matthew A. Kenny, Sean M. Bauer, Michael J. Schulte, Katherine Compton
2010Early Prediction of Hardware Complexity in HLL-to-HDL Translation.
Alessandro Cilardo, Paolo Durante, Carmelo Lofiego, Antonino Mazzeo
2010Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial Computation.
Gustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña
2010Efficient FPGA Resynthesis Using Precomputed LUT Structures.
Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu
2010Efficiently Generating FPGA Configurations through a Stack Machine.
Fatma Abouelella, Karel Bruneel, Dirk Stroobandt
2010Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains.
Thomas B. Preußer, Rainer G. Spallek
2010Erlang Inspired Hardware.
Paulo Ferreira, João Canas Ferreira, José Carlos Alves
2010Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC.
Hung-Manh Pham, Sébastien Pillement, Didier Demigny
2010Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters.
Amir Hossein Gholamipour, Fadi J. Kurdahi, Ahmed M. Eltawil, Mazen A. R. Saghir
2010Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection Systems.
Salvatore Pontarelli, Claudio Greco, Enrico Nobile, Simone Teofili, Giuseppe Bianchi
2010Exploration of Short Reads Genome Mapping in Hardware.
Edward Fernandez, Walid A. Najjar, Elena Yavorska Harris, Stefano Lonardi
2010FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators.
Muhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé
2010FPGA Based Engines for Genetic and Memetic Algorithms.
Pedro V. Santos, José C. Alves
2010FPGA Based Network Traffic Analysis Using Traffic Dispersion Patterns.
Faisal Khan, Maya B. Gokhale, Chen-Nee Chuah
2010FPGA Implementations of the Round Two SHA-3 Candidates.
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Máire O'Neill, William P. Marnane
2010FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers.
David B. Thomas, Wayne Luk
2010FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory Networks.
Ricardo S. Ferreira, Julio C. Goldner Vendramini
2010Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video.
Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto
2010Field Programmable Gate Array Implementation of Parts-Based Object Detection for Real Time Video Applications.
Deborah Goshorn, Junguk Cho, Ryan Kastner, Shahnam Mirzaei
2010Finding System-Level Information and Analyzing Its Correlation to FPGA Placement.
Farnaz Gharibian, Lesley Shannon, Peter Jamieson
2010First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells.
Masahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
2010Flexible and Modular Support for Timing Functions in High Performance Networking Acceleration.
Christopher E. Neely, Gordon J. Brebner, Weijia Shang
2010GPU Versus FPGA for High Productivity Computing.
David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung
2010General Purpose Computing with Reconfigurable Acceleration.
Anthony Brandon, Ioannis Sourdis, Georgi Nedeltchev Gaydadjiev
2010Generation of Deterministic MCU/FPGA Hybrid Systems from UML Activities.
Ruediger Willenberg, Zamira Daw, Christian Englert, Marcus Vetter
2010Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA.
Ghizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin
2010High Density Asynchronous LUT Based on Non-volatile MRAM Technology.
Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2010High-Performance Integer Factoring with Reconfigurable Devices.
Ralf Zimmermann, Tim Güneysu, Christof Paar
2010IP Based Configurable SIMD Massively Parallel SoC.
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser
2010Implementing Rainbow Tables in High-End FPGAs for Super-Fast Password Cracking.
Kostas Theocharoulis, Ioannis Papaefstathiou, Charalampos Manifavas
2010Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers.
Leandro Möller, Peter Fischer, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner
2010Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis.
Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent E. Nelson, Michael Rice, Michael J. Wirthlin
2010International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy
2010Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures.
Lyonel Barthe, Pascal Benoit, Lionel Torres
2010LavA: An Open Platform for Rapid Prototyping of MPSoCs.
Matthias Meier, Michael Engel, Matthias Steinkamp, Olaf Spinczyk
2010MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology.
Sascha Mühlbach, Martin Brunner, Christopher Roblee, Andreas Koch
2010Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays.
Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck
2010Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA.
Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides
2010Memory System for a Dynamically Adaptable Pixel Stream Architecture.
Nicolas Ngan, Geoffroy Marpeaux, Eva Dokládalová, Mohamed Akil, François Contou-Carrère
2010Multiplicative Square Root Algorithms for FPGAs.
Florent de Dinechin, Mioara Joldes, Bogdan Pasca, Guillaume Revy
2010NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA 'Threads' for Rapid HW/SW Systems Prototyping.
Hari Angepat, Gage Eads, Christopher Craik, Derek Chiou
2010On Identifying Patterns in Code Repositories to Assist the Generation of Hardware Templates.
Adriano K. Sanches, João M. P. Cardoso
2010On Identifying Segments of Traces for Dynamic Compilation.
João Bispo, João M. P. Cardoso
2010Online Routing Fault Detection for Reconfigurable NoC.
Cédric Killian, Camel Tanougast, Fabrice Monteiro, Abbas Dandache
2010OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices.
Mingjie Lin, Ilia A. Lebedev, John Wawrzynek
2010Optimization of Regular Expression Pattern Matching Circuit Using At-Most Two-Hot Encoding on FPGA.
SangKyun Yun, KyuHee Lee
2010Parallel Hardware Implementation of Connected Component Tree Computation.
Petr Matas, Eva Dokládalová, Mohamed Akil, Vjaceslav Georgiev, Martin Poupa
2010Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs).
Doris Chen, Deshanand P. Singh
2010Parallelizing Simulated Annealing-Based Placement Using GPGPU.
Alexander Choong, Rami Beidas, Jianwen Zhu
2010Pipelined FPGA Adders.
Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca
2010Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra Prediction.
Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu
2010PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex Systems.
Dam Sunwoo, Gene Y. Wu, Nikhil A. Patil, Derek Chiou
2010Proof-Carrying Hardware: Runtime Formal Verification for Secure Dynamic Reconfiguration.
Stephanie Drzevitzky
2010Rapid Application Development on Multi-processor Reconfigurable Systems.
Linfeng Ye, Jean-Philippe Diguet, Guy Gogniat
2010Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGA.
Felipe Restrepo-Calle, Antonio Martínez-Álvarez, Francisco R. Palomo, Hipólito Guzmán-Miranda, M. A. Aguirre, Sergio Cuenca-Asensi
2010Real-Time Classification of Multimedia Traffic Using FPGA.
Weirong Jiang, Maya B. Gokhale
2010Real-Time Fault Detection and Diagnostics Using FPGA-based Architectures.
Nathan Naber, Thomas Getz, Yong Kim, James Petrosky
2010Real-Time Processing of Contrast Limited Adaptive Histogram Equalization on FPGA.
Kentaro Kokufuta, Tsutomu Maruyama
2010Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options.
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
2010Reconfigurable Hardware for Power-over-Fiber Applications.
Michael Dreschmann, Michael Hübner, Moritz Röger, Oliver Sander, Christos Klamouris, Jürgen Becker, Wolfgang Freude, Juerg Leuthold
2010Reconfigurable Systems for the Zuker and Predator Algorithms for Secondary Structure Prediction of Genetic Data.
Miltiadis Smerdis, Panagiotis Dagritzikos, Grigorios Chrysos, Euripides Sotiriades, Apostolos Dollas
2010Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique.
Antonin Hermanek, Michal Kunes, Milan Tichý
2010Robust FPGA Design under Variations.
Akhilesh Kumar, Mohab Anis
2010Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine.
Stephen Wray, Wayne Luk, Peter R. Pietzuch
2010Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs.
Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva
2010Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGA.
Florian Devic, Lionel Torres, Benoît Badrignans
2010Self-Aware Adaptation in FPGA-based Systems.
Filippo Sironi, Marco Triverio, Henry Hoffmann, Martina Maggio, Marco D. Santambrogio
2010Self-Test and Adaptation for Random Variations in Reliability.
Kenneth M. Zick, John P. Hayes
2010SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing.
Kristian Stevens, Henry Chen, Terry Filiba, Peter L. McMahon, Yun S. Song
2010Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration.
Christian Beckhoff, Dirk Koch, Jim Tørresen
2010Software Managed Distributed Memories in MPPAs.
Robin Panda, Jimmy Xu, Scott Hauck
2010Sum of Absolute Difference Implementations for Image Processing on FPGAs.
Hiroaki Niitsuma, Tsutomu Maruyama
2010Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs.
Syed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Laurent Rouge
2010Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic.
Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2010Test Compression for Dynamically Reconfigurable Processors.
Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Koichiro Furuta
2010Thermal Gradient Aware Clock Skew Scheduling for FPGAs.
Sungmin Bae, Narayanan Vijaykrishnan
2010Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA.
Vijay K. Sirigir, Khawla Alzoubi, Daniel G. Saab, Fatih Kocan, Massood Tabib-Azar
2010Using Hard Macros to Reduce FPGA Compilation Time.
Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin