FPL B

142 papers

YearTitle / Authors
200919th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic
Martin Danek, Jiri Kadlec, Brent E. Nelson
2009A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM).
Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou, Apostolos Dollas
2009A biophysically accurate floating point somatic neuroprocessor.
Yiwei Zhang, José L. Núñez-Yáñez, Joe McGeehan, Edward Regan, Stephen Kelly
2009A comparison of FPGA and FPAA technologies for a signal processing application.
Roberto Selow, Heitor S. Lopes, Carlos Raimundo Erig Lima
2009A dynamically reconfigurable parallel pixel processing system.
Daniel Llamocca, Marios S. Pattichis, G. Alonzo Vera
2009A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems.
Joannis Sotiropoulos, Ioannis Papaefstathiou
2009A highly scalable Restricted Boltzmann Machine FPGA implementation.
Sang Kyun Kim, Lawrence C. McAfee, Peter Leonard McMahon, Kunle Olukotun
2009A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model.
Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala
2009A multi-FPGA architecture for stochastic Restricted Boltzmann Machines.
Daniel Le Ly, Paul Chow
2009A multi-layered XML schema and design tool for reusing and integrating FPGA IP.
Adam Arnesen, Nathan Rollins, Michael J. Wirthlin
2009A new deadlock-free fault-tolerant routing algorithm for NoC interconnections.
Slavisa Jovanovic, Camel Tanougast, Serge Weber, Christophe Bobda
2009A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs.
Xabier Iturbe, Mikel Azkarate-askasua, Imanol Martinez, Jon Pérez, Armando Astarloa
2009A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support.
Konstantinos Kyriakoulakos, Dionisios N. Pnevmatikatos
2009A novel states recovery technique for the TMR softcore processor.
Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi
2009A radix-8 complex divider for FPGA implementation.
Dong Wang, Milos D. Ercegovac, Nanning Zheng
2009A reconfigurable FIR/FFT unit for wireless telecommunication systems.
Maroun Ojail, Raphaël David, Stéphane Chevobbe, Didier Demigny
2009A reconfigurable architecture for the Phylogenetic Likelihood Function.
Nikolaos Alachiotis, Alexandros Stamatakis, Euripides Sotiriades, Apostolos Dollas
2009A runtime relocation based workflow for self dynamic reconfigurable systems design.
Marco D. Santambrogio, Massimo Morandi, Marco Novati, Donatella Sciuto
2009A self-reconfiguring architecture supporting multiple objective functions in genetic algorithms.
Charalampos Effraimidis, Kyprianos Papadimitriou, Apostolos Dollas, Ioannis Papaefstathiou
2009A toolset for the analysis and optimization of motion estimation algorithms and processors.
Trevor Spiteri, George Vafiadis, José Luis Núñez-Yáñez
2009A virus scanning engine using a parallel finite-input memory machine and MPUs.
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura
2009Accelerating HMMER search using FPGA.
Toyokazu Takagi, Tsutomu Maruyama
2009Acceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3.
Enrique Cantó, Mariano Fons, Mariano López-García, Rafael Ramos-Lara
2009An ASIC perspective on FPGA optimizations.
Andreas Ehliar, Dake Liu
2009An FPGA based verification platform for HyperTransport 3.x.
Heiner Litz, Holger Fröning, Maximilian Thürmer, Ulrich Brüning
2009An FPGA design for evaluating score function in protein energy calculation.
Jose Manuel Romero-Ximil, Arturo Díaz-Pérez
2009An FPGA-based embedded wideband audio codec system.
Chang Choo, Bhavya Bambhania, Woon Seob So, In Ki Hwang, Do Young Kim
2009An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure.
Tobias Schumacher, Christian Plessl, Marco Platzner
2009An analytical model relating FPGA architecture and place and route runtime.
Scott Y. L. Chin, Steven J. E. Wilton
2009An approach to system-wide fault tolerance for FPGAs.
Jano Gebelein, Heiko Engel, Udo Kebschull
2009An efficient reconfigurable architecture to implement dense stereo vision algorithm using high-level synthesis.
Mario Alberto Ibarra-Manzano, Michel Devy, Jean-Louis Boizard, Pierre Lacroix, Jean-Yves Fourniols
2009An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs.
Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009Area estimation and optimisation of FPGA routing fabrics.
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2009Automatic generation of FPGA hardware accelerators using a domain specific language.
Ricardo Menotti, João M. P. Cardoso, Marcio Merino Fernandes, Eduardo Marques
2009Binary Synthesis with multiple memory banks targeting array references.
Yosi Ben-Asher, Nadav Rotem
2009Bitstream compression through frame removal and partial reconfiguration.
Benjamin Sellers, Jonathan Heiner, Michael J. Wirthlin, Jeff Kalb
2009Building heterogeneous reconfigurable systems using threads.
Jason Agron, David Andrews
2009CNP: An FPGA-based processor for Convolutional Networks.
Clément Farabet, Cyril Poulet, Jefferson Y. Han, Yann LeCun
2009CREMA: A coarse-grain reconfigurable array with mapping adaptiveness.
Fabio Garzia, Waqar Hussain, Jari Nurmi
2009Clock duplicity for high-precision timestamping in Gigabit Ethernet.
Carles Nicolau, Dolors Sala, Enrique Cantó
2009Clock gating architectures for FPGA power reduction.
Safeen Huda, Muntasir Mallick, Jason Helge Anderson
2009Coarse-grained dynamically reconfigurable architecture with flexible reliability.
Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye
2009Compact FPGA implementation of Camellia.
Panasayya Yalla, Jens-Peter Kaps
2009Comparing fine-grained performance on the Ambric MPPA against an FPGA.
Brad L. Hutchings, Brent E. Nelson, Stephen West, Reed Curtis
2009Compensating for variability in FPGAs by re-mapping and re-placement.
N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung
2009Compiler assisted runtime task scheduling on a reconfigurable computer.
Mojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels
2009Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator.
Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano
2009Cooperative multithreading in dynamically reconfigurable systems.
Enno Lübbers, Marco Platzner
2009Customizable domain-specific computing.
Jason Cong
2009DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs.
Rajesh Velegalati, Jens-Peter Kaps
2009Data parallel FPGA workloads: Software versus hardware.
Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2009Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes.
Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths.
Dimitrios Kontos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos
2009Dynamic Polymorphic Reconfiguration for anti-tamper circuits.
Roy Porter, Samuel J. Stone, Yong C. Kim, Jeffrey Todd McDonald, LaVern A. Starman
2009Dynamic reconfigurable mixed-signal architecture for safety critical applications.
Romuald Girardey, Michael Hübner, Jürgen Becker
2009Dynamic reconfiguration system for real-time video processing.
Saya Hinaga, Yoshiki Yamaguchi, Tetsuhiko Yao, Tohru Kawabe
2009Efficient AES S-boxes implementation for non-volatile FPGAs.
Lubos Gaspar, Milos Drutarovský, Viktor Fischer, Nathalie Bochard
2009Efficient particle-pair filtering for acceleration of molecular dynamics simulation.
Matt Chiu, Martin C. Herbordt
2009Efficient techniques and methodologies for embedded system design usign free hardware and open standards.
Jose Ignacio Villar, Jorge Juan, Manuel J. Bellido
2009Emulating Spiking Neural Networks for edge detection on FPGA hardware.
Brendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire, Qingxiang Wu
2009Enhanced gradient-based motion vector coprocessor.
Guillermo Botella Juan, Antonio García Ríos, Uwe Meyer-Bäse, Manuel Rodríguez, María C. Molina, Luís Parrilla Roure
2009Enhancements to FPGA design methodology using streaming.
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2009Exploiting fast carry-chains of FPGAs for designing compressor trees.
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2009Exploiting synchronous placement for asynchronous circuits onto commercial FPGAs.
Maurizio Tranchero, Leonardo Maria Reyneri
2009Exploring reconfigurable architectures for explicit finite difference option pricing models.
Qiwei Jin, David B. Thomas, Wayne Luk
2009FPGA accelerating three QR decomposition algorithms in the unified pipelined framework.
Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu
2009FPGA challenges and opportunities at 40nm and beyond.
Vaughn Betz
2009FPGA partial reconfiguration via configuration scrubbing.
Jonathan Heiner, Benjamin Sellers, Michael J. Wirthlin, Jeff Kalb
2009FPGA supercomputing platforms: A survey.
Mariette Awad
2009FPGA support for satellite computations of hyper spectral images.
Carlos González, Daniel Mozos, Javier Resano
2009FPGA-accelerated Information Retrieval: High-efficiency document filtering.
Wim Vanderbauwhede, Leif Azzopardi, Mahmoud Moadeli
2009FPGA-accelerated retinal vessel-tree extraction.
Alejandro Nieto, Víctor M. Brea, David López Vilariño
2009FPGA-based acceleration of neural network for ranking in web search engine with a streaming architecture.
Jing Yan, Ningyi Xu, Xiongfei Cai, Rui Gao, Yu Wang, Rong Luo, Feng-Hsiung Hsu
2009FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic.
Roberto Gutiérrez, Javier Valls, Asuncion Perez-Pascual
2009Fast critical sections via thread scheduling for FPGA-based multithreaded processors.
Martin Labrecque, J. Gregory Steffan
2009Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.
Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano
2009General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems.
Josef Angermeier, Abdulazim Amouri, Jürgen Teich
2009Generating high-performance custom floating-point pipelines.
Florent de Dinechin, Cristian Klein, Bogdan Pasca
2009Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems.
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
2009Hardware implementation of MPI_Barrier on an FPGA cluster.
Shanyuan Gao, Andrew G. Schmidt, Ron Sass
2009High speed fixed point dividers for FPGAs.
Gustavo Sutter, Jean-Pierre Deschamps
2009High-level programming of coarse-grained reconfigurable architectures.
Zain-ul-Abdin
2009Hot-Swapping architecture extension for mitigation of permanent functional unit faults.
Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura
2009IP protection in Partially Reconfigurable FPGAs.
Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz
2009Implementation of a reconfigurable Fast Fourier Transform application to digital terrestrial television broadcasting.
Florent Camarda, Jean-Christophe Prévotet, Fabienne Nouvel
2009Improving logic density through synthesis-inspired architecture.
Jason Helge Anderson, Qiang Wang
2009Improving the memory footprint and runtime scalability of FPGA CAD algorithms.
Scott Y. L. Chin, Steven J. E. Wilton
2009Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators.
Abhranil Maiti, Patrick Schaumont
2009In field, energy-performance tunable FPGA architectures.
Bita Nezamfar, Mark Horowitz
2009In search of agile hardware.
Peter Athanas
2009Increasing stability and distinguishability of the digital fingerprint in FPGAs through input word analysis.
Hiren J. Patel, Yong C. Kim, Jeffrey Todd McDonald, LaVern A. Starman
2009Large multipliers with fewer DSP blocks.
Florent de Dinechin, Bogdan Pasca
2009Low power techniques for Motion Estimation hardware.
Caglar Kalaycioglu, Onur Can Ulusel, Ilker Hamzaoglu
2009Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs.
Rohit Kumar, Ann Gordon-Ross
2009Mapping basic prefix computations to fast carry-chain structures.
Thomas B. Preußer, Rainer G. Spallek
2009Mems optically reconfigurable gate array.
Hironobu Morita, Minoru Watanabe
2009Modeling post-techmapping and post-clustering FPGA circuit depth.
Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2009Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs.
Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano
2009MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.
Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano
2009Multi-terminal BDD synthesis and applications.
Petr Mikusek
2009Multigigabit network traffic processing.
Jiri Halak
2009Noise impact of single-event upsets on an FPGA-based digital filter.
Brian H. Pratt, Michael J. Wirthlin, Michael P. Caffrey, Paul S. Graham, Keith Morgan
2009Novel strategies for hardware acceleration of frequent itemset mining with the apriori algorithm.
David W. Thöni, Alfred Strey
2009Numerically controlled oscillators using linear approximation.
Hans-Jörg Pfleiderer, Stefan Lachowicz
2009Off-line placement of hardware tasks on FPGA.
Ikbel Belaid, Fabrice Muller, Maher Benjemaa
2009Operation scheduling for FPGA-based reconfigurable computers.
Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
2009Optimal runtime reconfiguration strategies for systolic arrays.
Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain
2009Optimising designs by combining model-based and pattern-based transformations.
Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides
2009Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation.
Christopher Claus, Robert Huitl, Joachim Rausch, Walter Stechele
2009Performance comparison of FPGA, GPU and CPU in image processing.
Shuichi Asano, Tsutomu Maruyama, Yoshiki Yamaguchi
2009Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors.
Nachiket Kapre, André DeHon
2009Performance metrics for hybrid multi-tasking systems.
Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton
2009Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA.
Tomasz Kryjak, Marek Gorgon
2009Program-driven fine-grained power management for the reconfigurable mesh.
Heiner Giefers, Marco Platzner
2009Proteus: An architectural synthesis tool based on the stream programming paradigm.
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier, Abelardo López-Lagunas
2009RISPP: A run-time adaptive reconfigurable embedded processor.
Lars Bauer, Muhammad Shafique, Jörg Henkel
2009Random numbers generation: Investigation of narrowtransitions suppression on FPGA.
Vladimir Rozic, Ingrid Verbauwhede
2009Rapid design exploration framework for application-aware customization of soft core processors.
Alok Prakash, Siew Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan
2009Real-time processing of local contrast enhancement on FPGA.
Kentaro Kokufuta, Tsutomu Maruyama
2009Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space.
Adam Jacobs, Alan D. George, Grzegorz Cieslewski
2009Reconfiguration-based time-to-digital converter for Virtex FPGAs.
Ángel Quirós-Olozábal, Juan Manuel Barrientos-Villar, Ma de los Ángeles Cifredo Chacón
2009Recursion in reconfigurable computing: A survey of implementation approaches.
Iouliia Skliarova, Valery Sklyarov
2009Replace: An incremental placement algorithm for field programmable gate arrays.
David Leong, Guy G. Lemieux
2009Run-time Partial Reconfiguration speed investigation and architectural design space exploration.
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch
2009Run-time resource management in fault-tolerant network on reconfigurable chips.
Mohammad Hosseinabady, José L. Núñez-Yáñez
2009SVM speaker verification system based on a low-cost FPGA.
Rafael Ramos-Lara, Mariano López-García, Enrique F. Cantó-Navarro, Luis Puente-Rodriguez
2009Secure FPGA technologies and techniques.
An Braeken, Serge Kubera, Frederik Trouillez, Abdellah Touhafi, Nele Mentens, Jo Vliegen
2009Self-organizing multi-cue fusion for FPGA-based embedded imaging.
Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich
2009Sharf: An FPGA-based customizable processor architecture.
Cem Savas Bassoy, Henning Manteuffel, Friedrich Mayer-Lindenberg
2009Soft errors in Flash-based FPGAs: Analysis methodologies and first results.
Niccolò Battezzati, Filomena Decuzzi, Luca Sterpone, Massimo Violante
2009Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol.
Diana Göhringer, Bin Liu, Michael Hübner, Jürgen Becker
2009Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays.
Brian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck
2009Synthesis of the SR programming language for complex FPGAs.
Nick Gasson, Neil C. Audsley
2009The educational processor Sweet-16.
Venelin Angelov, Volker Lindenstruth
2009The evolution of architecture exploration of programmable devices.
Jonathan Rose
2009Towards a unique FPGA-based identification circuit using process variations.
Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf
2009Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming.
Kaveh Aasaraai, Andreas Moshovos
2009Tracking elephant flows in internet backbone traffic with an FPGA-based cache.
Martin Zádník, Marco Canini, Andrew W. Moore, David J. Miller, Wei Li
2009Using 3D integration technology to realize multi-context FPGAs.
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009Using C-to-gates to program streaming image processing kernels efficiently on FPGAs.
Kristof Denolf, Stephen Neuendorffer, Kees A. Vissers
2009Virtex-6 and Spartan-6, plus a look into the future.
Peter Alfke
2009sFPGA2 - A scalable GALS FPGA architecture and design methodology.
Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli