FPL B

154 papers

YearTitle / Authors
2008A comparison of embedded reconfigurable video-processing architectures.
Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich
2008A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor.
Lars Bauer, Muhammad Shafique, Jörg Henkel
2008A configurable and programmable motion estimation processor for the H.264 video codec.
José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras
2008A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck.
Claudio Brunelli, Fabio Garzia, Carmelo Giliberto, Jari Nurmi
2008A dynamic temperature control simulation system for FPGAs.
Shilpa Bhoj, Dinesh Bhatia
2008A flexible and reliable embedded system for detector control in a high energy physics experiment.
Tobias Krawutschke
2008A hardware compilation flow for instance-specific VLIW cores.
Markus Koester, Wayne Luk, Geoffrey Brown
2008A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA.
Andreas Ehliar, Per Karlström, Dake Liu
2008A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor.
Andre Guntoro, Manfred Glesner
2008A link removal methodology for Networks-on-Chip on reconfigurable systems.
Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2008A low overhead fault tolerant FPGA with new connection box.
Fujie Wong, Yajun Ha
2008A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput.
Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker
2008A new methodology for debugging and validation of soft cores.
Christian Hochberger, Alexander Weiss
2008A non-volatile run-time FPGA using thermally assisted switching MRAMS.
Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham Hassoune
2008A portable abstraction layer for hardware threads.
Enno Lübbers, Marco Platzner
2008A rate-based prefiltering approach to blast acceleration.
Panagiotis Afratis, Euripides Sotiriades, Grigorios Chrysos, Sotiria Fytraki, Dionisios N. Pnevmatikatos
2008A reconfigurable accelerator for quantum computations.
Michail Zampetakis, Vasilis Samoladas, Apostolos Dollas
2008A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays.
Theepan Moorthy, Andy Ye
2008A technique for minimizing power during FPGA placement.
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-Chung Hsu, Arun Kundu, Andrew A. Kennings
2008A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.
Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera
2008A versatile hardware architecture for a CFAR detector based on a linear insertion sorter.
Roberto Perez-Andrade, René Cumplido, Claudia Feregrino-Uribe, Fernando Martin del Campo
2008ATCA-based computation platform for data acquisition and triggering in particle physics experiments.
Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch
2008Acceleration of a production rigid molecule docking code.
Bharat Sukhwani, Martin C. Herbordt
2008Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems.
Wenyin Fu, Katherine Compton
2008Adaptive precision technique for genetic algorithms.
Gary Chun Tak Chow
2008An FPGA architecture for the Pagerank eigenvector problem.
Séamas McGettrick, Dermot Geraghty, Ciarán McElroy
2008An FPGA-based high-speed, low-latency trigger processor for high-energy physics.
Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth
2008An FPGA-based implementation of the MINRES algorithm.
David Boland, George A. Constantinides
2008An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC.
Jason Wu, John Williams, Neil W. Bergmann
2008An analytical model describing the relationships between logic architecture and FPGA density.
Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2008An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects.
Hanyu Liu, Xiaolei Chen, Yajun Ha
2008An efficient run-time router for connecting modules in FPGAS.
Jorge Surís, Cameron D. Patterson, Peter Athanas
2008An element-by-element preconditioned Conjugate Gradient solver of 3D tetrahedral finite elements on an FPGA coprocessor.
Jing Hu, Steven F. Quigley, Andrew Chan
2008An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture.
Kimon Karras, Elias S. Manolakos
2008An integrated debugging environment for FPGA computing platforms.
Kevin Camera, Robert W. Brodersen
2008An optimization method of DMA transfer for a general purpose reconfigurable machine.
Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell
2008An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation.
Stanislaw Deniziak, Mariusz Wisniewski
2008Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor.
Young-Su Kwon, Bontae Koo, Nak-Woong Eum
2008Application-specific reconfigurable processors.
Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll
2008Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching.
George Kornaros, Wolfram Lautenschlaeger, Matthias Sund, Helen-Catherine Leligou
2008Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures.
Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig
2008Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS.
Gang Zhou, Li Li, Harald Michalik
2008Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.
Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst
2008Automatic generation of run-time parameterizable configurations.
Karel Bruneel, Dirk Stroobandt
2008BOUNCE, a new approach to measure sub-nanosecond time intervals.
Ralf Joost, Ralf Salomon
2008Bio-inspiration helps computers: A new machine.
Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert
2008Bitstream compression techniques for Virtex 4 FPGAs.
Radu Andrei Stefan, Sorin Dan Cotofana
2008Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems.
Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda
2008CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures.
Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, Susan J. Eggers
2008CVC: The C to RTL compiler for callback-based verification model.
Yasuhiro Ito, Yutaka Sugawara, Mary Inaba, Kei Hiraki
2008Chosen-message SPA attacks against FPGA-based RSA hardware implementations.
Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2008Cluster architecture based on low cost reconfigurable hardware.
César Pedraza, Emilio Castillo, Javier Castillo, Cristobal Camarero, José Luis Bosque, José Ignacio Martínez, Rafael Menéndez de Llano
2008Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC.
Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez
2008Coarse-grained reconfiguration.
Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008Combating process variation on FPGAS with a precise at-speed delay measurement method.
Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole
2008Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework.
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2008Comparing throughput and power consumption in both sequential and reconfigurable processors.
Kevin K. Liu, Charles B. Cameron, Antal A. Sarkady
2008Compiled hardware acceleration of Molecular Dynamics code.
Jason R. Villarreal, Walid A. Najjar
2008Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs.
Betul Buyukkurt, Walid A. Najjar
2008Connected components analysis of streamed images.
Donald G. Bailey, Christopher T. Johnston, Ni Ma
2008Convergence analysis of run-time distributed optimization on adaptive systems using game theory.
Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres
2008Creating unique identifiers on field programmable gate arrays using natural processing variations.
James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington
2008Customized Reconfigurable Interconnection Networks for multiple application SOCS.
Hongbing Fan, Jason Ernst, Yu-Liang Wu
2008Data path driven waveform-like reconfiguration.
Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker
2008Decimal multiplier on FPGA using embedded binary multipliers.
Horácio C. Neto, Mário P. Véstias
2008Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA.
Haiting Tian, Shakith Fernando, Hock Wei Soon, Yajun Ha, Nanguang Chen
2008Digital hilbert transformers for FPGA-based phase-locked loops.
Martin Kumm, M. Shahab Sanjari
2008Direct sigma-delta modulated signal processing in FPGA.
Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng
2008EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs.
Oliver A. Pfänder, Hans-Jörg Pfleiderer
2008Efficient FPGA mapping of Gilbert's algorithm for SVM training on large-scale classification problems.
Markos Papadonikolakis, Christos-Savvas Bouganis
2008Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.
Diego Pedro Morales, Antonio García, Alberto J. Palma, Miguel Ángel Carvajal, Encarnación Castillo, Luis F. Capitán-Vallvey
2008Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis.
Tim Güneysu, Christof Paar, Gerd Pfeiffer, Manfred Schimmler
2008Enhancing security of ring oscillator-based trng implemented in FPGA.
Viktor Fischer, Florent Bernard, Nathalie Bochard, Michal Varchola
2008Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor.
Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez
2008Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization.
Katarina Paulsson, Michael Hübner, Jürgen Becker
2008Exploring FPGA network on chip implementations across various application and network loads.
Graham Schelle, Dirk Grunwald
2008Exploring compact design on high throughput coarse grained reconfigurable architectures.
Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka
2008FPGA acceleration of Monte-Carlo based credit derivative pricing.
Alexander Kaganov, Paul Chow, Asif Lakhany
2008FPGA acceleration of quasi-Monte Carlo in finance.
Nathan A. Woods, Tom Van Court
2008FPGA family composition and effects of specialized blocks.
Pongstorn Maidee, Nagib Hakim, Kia Bazargan
2008FPGA implementation of a flexible decoder for long LDPC codes.
Christiane Beuschel, Hans-Jörg Pfleiderer
2008FPGA interconnect design using logical effort.
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
2008FPGA interconnect sizing using extended logical effort model.
Haile Yu
2008FPGA: The future platform for transforming, transporting and computing data.
Ivo Bolsens
2008FPGAS in high energy physics experiments at CERN.
L. Musa
2008FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008
2008Fast and accurate resource estimation of RTL-based designs targeting FPGAS.
Paul Schumacher, Pradip Jha
2008Fast toggle rate computation for FPGA circuits.
Tomasz S. Czajkowski, Stephen Dean Brown
2008Fault tolerant methods for reliability in FPGAs.
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
2008File system access from reconfigurable FPGA hardware processes in BORPH.
Hayden Kwok-Hay So, Robert W. Brodersen
2008Fine grain reconfigurable architectures.
Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008Floating point datapath synthesis for FPGAs.
Martin Langhammer
2008GICS: Generic interconnection system.
Tamas Malek, Tomás Martínek, Jan Korenek
2008Generation of partial FPGA configurations at run-time.
Miguel Lino Silva, João Canas Ferreira
2008High-performance fpga-based floating-point adder with three inputs.
Andre Guntoro, Manfred Glesner
2008High-speed regular expression matching engine using multi-character NFA.
Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kamiya
2008How fast is an FPGA in image processing?
Takashi Saegusa, Tsutomu Maruyama, Yoshiki Yamaguchi
2008Hyperreconfigurable architectures.
Sebastian Lange, Martin Middendorf
2008IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration.
Ahmad Sghaier, Shawki Areibi, Robert D. Dony
2008Increasing the level of abstraction in FPGA-based designs.
Martin Danek, Jiri Kadlec, Roman Bartosinski, Lukas Kohout
2008Instruction buffer mode for multi-context Dynamically Reconfigurable Processors.
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano
2008Interface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor.
Syed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede
2008Keynote: High performance computing based on FPGAS.
O. Wohlmuth
2008Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory.
Meikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha
2008Loop unrolling and shifting for reconfigurable architectures.
Ozana Silvia Dragomir, Todor P. Stefanov, Koen Bertels
2008Low-latency high-bandwidth HW/SW communication in a virtual memory environment.
Holger Lange, Andreas Koch
2008MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.
Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong
2008Mapping and scheduling with task clustering for heterogeneous computing systems.
Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong
2008Memory access parallelisation in high-level language compilation for reconfigurable adaptive computers.
Hagen Gädke, Florian Stock, Andreas Koch
2008Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip.
Matthew Shelburne, Cameron D. Patterson, Peter Athanas, Mark Jones, Brian S. Martin, Ryan Fong
2008Mining Association Rules with systolic trees.
Song Sun, Joseph Zambreno
2008Modeling recursion data structures for FPGA-based implementation.
Spyridon Ninos, Apostolos Dollas
2008NOC architecture design for multi-cluster chips.
Henrique C. Freitas, Philippe Olivier Alexandre Navaux, Tatiana Gadelha Serra dos Santos
2008Network processors.
Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf
2008New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach.
Diana Göhringer, Michael Hübner, Thomas Perschke, Jürgen Becker
2008No-break dynamic defragmentation of reconfigurable devices.
Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich
2008Novel FPGA based Haar classifier face detection algorithm acceleration.
Changjian Gao, Shih-Lien Lu
2008Numerical function generators using bilinear interpolation.
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
2008On the design parameters of runtime reconfigurable systems.
Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle
2008On-the-fly attestation of reconfigurable hardware.
Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa
2008Operating system support for online partial dynamic reconfiguration management.
Marco D. Santambrogio, Vincenzo Rana, Donatella Sciuto
2008Parallel hardware objects for dynamically partial reconfiguration.
Norbert Abel, Frederik Grüll, Nick Meier, Andreas Beyer, Udo Kebschull
2008Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.
Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
2008Polymorphic wavelet architectures using reconfigurable hardware.
Amit Pande, Joseph Zambreno
2008Power efficient DSP datapath configuration methodology for FPGA.
Stephen McKeown, Roger F. Woods, John McAllister
2008Power reduction techniques for Dynamically Reconfigurable Processor Arrays.
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano
2008Practical implementation of a network-based stochastic biochemical simulation system on an FPGA.
Masato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano
2008Rapid estimation of power consumption for hybrid FPGAs.
Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
2008ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS.
Dirk Koch, Christian Beckhoff, Jürgen Teich
2008Real-time image super resolution using an FPGA.
Oliver Bowen, Christos-Savvas Bouganis
2008Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems.
Alexander Danilin, Sergei Sawitzki, Erik Rijshouwer
2008Reconfigurable hardware: The holy grail of matching performance with programming productivity.
Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard
2008Reconfigurable many-cores with lean interconnect.
Heiner Giefers
2008Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks.
Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dudek, Thomas Dowrick, Liam McDaid
2008Reducing interconnection cost in coarse-grained dynamic computing through multistage network.
Ricardo S. Ferreira, Marcone Laure, Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro
2008Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform.
Vlad Mihai Sima, Elena Moscu Panainte, Koen Bertels
2008SAT-based resource binding for reducing critical path delays.
Kenshu Seto, Yuta Nonaka, Takuya Maruizumi, Yasuhiro Shiraki
2008Sampling from the exponential distribution using independent Bernoulli variates.
David B. Thomas, Wayne Luk
2008Scalable high performance computing on FPGA clusters using message passing.
Eoin Creedon, Michael Manzke
2008Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA.
Hoang Le, Weirong Jiang, Viktor K. Prasanna
2008Seamless design flow for reconfigurable systems.
Andreas Schallenberg, Achim Rettberg, Wolfgang Nebel, Franz-Josef Rammig
2008Searching for ET with FPGA'S.
Dan Werthimer
2008Secure FPGA configuration architecture preventing system downgrade.
Benoît Badrignans, Reouven Elbaz, Lionel Torres
2008Self-recofigurable embedded systems on Spartan-3.
Enrique Cantó, Francesc Fons, Mariano López-García
2008Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA.
Mamoun F. Al-Mistarihi
2008Shared reconfigurable architectures for CMPS.
Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi
2008Teaching FPGA system design via a remote laboratory facility.
Yamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, Ron Sass
2008The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays.
Ping Chen, Andy Ye
2008The hardware application platform of the hartes project.
Immacolata Colacicco, Giacomo Marchiori, Raffaele Tripiccione
2008Thermal aware FPGA architectures and CAD.
Shilpa Bhoj
2008Three-stage pipeline implementation for SHA2 using data forwarding.
Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi
2008Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system.
Brian Leung, Yan Pan, Christopher L. Schroeder, Seda Ogrenci Memik, Gokhan Memik, Mitra J. Z. Hartmann
2008Towards benchmarking energy efficiency of reconfigurable architectures.
Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa
2008sFPGA - A scalable switch based FPGA architecture and design methodology.
Shakith Fernando, Xiaolei Chen, Yajun Ha