FPL B

162 papers

YearTitle / Authors
2007A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP.
Brandon Harris, Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain
2007A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures.
Ashutosh Pal, M. Balakrishnan
2007A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator.
Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri
2007A Design Flow to Map Parallel Applications onto FPGAs.
Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser
2007A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs.
Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann
2007A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures.
Philipp Graf, Michael Hübner, Klaus D. Müller-Glaser, Jürgen Becker
2007A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem.
Shuichi Watanabe, Junji Kitamichi, Kenichi Kuroda
2007A High Speed License Plate Recognition System on an FPGA.
Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka
2007A Hybrid Reconfigurable Cluster-on-Chip Architecture With Message Passing Interface For Image Processing Applications.
Irfan Syed, John A. Williams, Neil W. Bergmann
2007A Load/Store Unit for a Memcpy Hardware Accelerator.
Stamatis Vassiliadis, Filipa Duarte, Stephan Wong
2007A Many-core Implementation based on the Reconfigurable Mesh Model.
Heiner Giefers, Marco Platzner
2007A Method for Fast Hardware Specialization at run-time.
Karel Bruneel, Peter Bertels, Dirk Stroobandt
2007A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays.
Ioannis Nousias, Sami Khawam, Mark Milward, Mark Muir, Tughrul Arslan
2007A New Scalable Hardware Architecture for RSA Algorithm.
Tamer Güdü
2007A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation.
Karthick Parashar, Nitin Chandrachoodan
2007A Pipeline Implementation of a Watershed Algorithm on FPGA.
Dang Ba Khac Trieu, Tsutomu Maruyama
2007A Power Estimation Model for an FPGA-based Softcore Processor.
Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll
2007A Quantitative Prediction Model for Hardware/Software Partitioning.
Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis
2007A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA.
Ludovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Barton B. Kincaid
2007A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA.
José M. Claver, P. Agustí, Germán León, Manel Canseco
2007A Run-time Reconfigurable Processor for Video Motion Estimation.
Miguel Ribeiro, Leonel Sousa
2007A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects.
Graham Schelle, Jeff Fifield, Dirk Grunwald
2007A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007A Time-Triggered Network-on-Chip.
Martin Schoeberl
2007A Unified Streaming Architecture for Real Time Face Detection and Gender Classification.
Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, Satish Mummareddy
2007A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores.
Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi
2007A floating-point Extended Kalman Filter implementation for autonomous mobile robots.
Vanderlei Bonato, Eduardo Marques, George A. Constantinides
2007A generalized and unified SPFD-based rewiring technique.
Pongstorn Maidee, Kia Bazargan
2007A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithm.
Vinay Sriram, David Kearney
2007A novel motion estimation power reduction technique.
Graeme Robert Stewart, David Renshaw, Martyn Riley
2007A resource optimized SoC Kit for FPGAs.
Gerald Hempel, Christian Hochberger
2007Accelerating Microblaze Floating Point Operations.
Jiri Kadlec, Roman Bartosinski, Martin Danek
2007Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer.
Jahyun J. Koo, Alan C. Evans, Warren J. Gross
2007Accelerating tool path computing in CAD/CAM: A FPGA architecture for turning lathe machining..
Antonio Jimeno-Morenilla, Antonio Martínez-Álvarez, Sergio A. Cuenca, José-Luis Sánchez-Romero
2007AdaBoost Engine.
Pavel Zemcík, Martin Zádník
2007Adaptive Thermoregulation for Applications on Reconfigurable Devices.
Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood
2007Adventures with a Reconfigurable Research Platform.
John Wawrzynek
2007Aggressive Loop Pipelining for Reconfigurable Architectures.
Ricardo Menotti, Eduardo Marques, João M. P. Cardoso
2007An Automatic Compilation Framework for Configurable Architectures.
Alberto Gallini, Lorenzo Pavesi, Claudio Ferretti, Alberto Rosti, Sara Bocchio
2007An Efficient Implementation of a 2D DWT on FPGA.
Michael Wisdom, Peter Lee
2007An Execution Model for Hardware/Software Compilation and its System-Level Realization.
Holger Lange, Andreas Koch
2007An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems.
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
2007An FPGA Based Memory Efficient Shared Buffer Implementation.
Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic
2007An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman Method.
Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko Konagaya
2007An FPGA Solver for Very Large SAT Problems.
Kenji Kanazawa, Tsutomu Maruyama
2007An OCM based shared Memory controller for Virtex 4.
Bas Breijer, Filipa Duarte, Stephan Wong
2007An area-efficient alternative to adaptive median filtering in FPGAs.
Zdenek Vasícek, Lukás Sekanina
2007An fpga based open source network-on-chip architecture.
Andreas Ehliar, Dake Liu
2007Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration.
John Shield, Peter Sutton, Philip Machanick
2007Applying Out-of-Core QR Decomposition Algorithms on FPGA-Based Systems.
Yi-Gang Tai, Chia-Tien Dan Lo, Kleanthis Psarris
2007Array Synthesis in SystemC Hardware Compilation.
Johan Ditmar, Steve McKeever
2007Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems.
William George Osborne, Ray C. C. Cheung, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer
2007Automatic Software Hardware Co-Design for Reconfigurable Computing Systems.
Proshanta Saha
2007Bringing High-Performance Reconfigurable Computing to Exact Computations.
Esam El-Araby, Iván González, Tarek A. El-Ghazawi
2007C++ based design flow for reconfigurable image processing systems.
Rob Beun, Irek Karkowski, Maarten Ditzel
2007Caching in Real-time Reconfiguration Port Scheduling.
Florian Dittmann, Stefan Frank
2007Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores.
Andrew G. Schmidt, Ron Sass
2007Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.
Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach
2007Clock-Aware Placement for FPGAs.
Julien Lamoureux, Steven J. E. Wilton
2007Compact AES-based Architecture for Symmetric Encryption, Hash Function, and Random Number Generation.
Ralf Laue, Oliver Kelm, Sebastian Schipp, Abdulhadi Shoufan, Sorin A. Huss
2007Compression system for the phonocardiographic signal.
F. Javier Toledo-Moreo, A. Legaz-Cano, J. Javier Martínez-Álvarez, Juan Martínez-Alajarín, Ramón Ruiz Merino
2007Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique.
Hagen Gädke, Andreas Koch
2007Confiuartion Management in the Context of Self Adapative Systems.
Yvan Eustache, Jean-Philippe Diguet
2007CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs.
Slavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber
2007DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator.
Yana Yankova, Koen Bertels, Georgi Kuzmanov, Georgi Gaydadjiev, Yi Lu, Stamatis Vassiliadis
2007Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays.
Yohei Hasegawa, Hideharu Amano
2007Design Space Exploration of the European Option Benchmark Using HyperStreams.
Gareth W. Morris, Matthew Aubury
2007Design of a hardware accelerator for fingerprint alignment.
Mariano Fons, Francisco Fons, Enrique Cantó, Mariano López-García
2007Discrete Event Simulation of Molecular Dynamics with Configurable Logic.
Josh Model, Martin C. Herbordt
2007Disjoint Pattern Enumeration for Custom Instructions Identification.
Pan Yu, Tulika Mitra
2007Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications.
Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
2007Dynamic Cache Switching in Reconfigurable Embedded Systems.
John Shield, Peter Sutton, Philip Machanick
2007Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System.
Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid
2007Dynamic Voltage Scaling in a FPGA-based System-on-Chip.
José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler
2007Dynamic reconfiguration management based on a distributed object model.
Julio Dondo, Fernando Rincón, Jesús Barba, Francisco Moya, Felix Jesús Villanueva, David Villa, Juan Carlos López
2007Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms.
Sven-Ole Voigt, Thomas Teufel
2007Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler.
Kristopher D. Peterson, Justin L. Tripp
2007Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips.
Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
2007Efficient FPGA-based multipliers for F_3^97 and F_3^(6*97).
Jamshid Shokrollahi, Elisa Gorla, Christoph Puttmann
2007Efficient Modeling and Floorplanning of Embedded-FPGA Fabric.
Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley
2007Efficient Priority-Queue Data Structure for Hardware Implementation.
Andrew Morton, Jeffrey Liu, Insop Song
2007Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion.
Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung
2007Embedded Programmable Logic Core Enhancements for System Bus Interfaces.
Bradley R. Quinton, Steven J. E. Wilton
2007Equivalence Verification of FPGA and Structured ASIC Implementations.
Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam
2007Evolutionary Search Applied to Reconfigurable Analogue Control.
Kester Dean Clegg, Susan Stepney, Tim Clarke
2007Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing.
Diego Pedro Morales, Antonio García, Alberto J. Palma, Antonio Martínez-Olmos, Encarnación Castillo
2007Exploiting Hardware and Software Low Power Techniques for Energy Efficient Co-scheduling in Dynamically Reconfigurable Systems.
Pao-Ann Hsiung, Chih-Wen Liu
2007Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support.
Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris
2007FPGA Implementation of 64-bit Exponential Function for HPC.
Ernest Jamro, Kazimierz Wiatr, Maciej Wielgosz
2007FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method.
Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano
2007FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM Memory.
David Gregg, Colm McSweeney, Ciarán McElroy, Fergal Connor, Séamas McGettrick, David Moloney, Dermot Geraghty
2007FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007
Koen Bertels, Walid A. Najjar, Arjan J. van Genderen, Stamatis Vassiliadis
2007Fast On-line Task Placement and Scheduling on Reconfigurable Devices.
Xuegong Zhou, Ying Wang, XunZhang Huang, Chenglian Peng
2007Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools.
Chee Sing Lee, Wei Ting Loke, Wenjuan Zhang, Yajun Ha
2007Fault Models and Yield Analysis for QCA-based PLAs.
Michael Crocker, Michael T. Niemier, Xiaobo Sharon Hu
2007Floating-Point Trigonometric Functions for FPGAs.
Jérémie Detrey, Florent de Dinechin
2007FlowContext: Flexible Platform for Multigigabit Stateful Packet Processing.
Martin Kosek, Jan Korenek
2007Formal Modeling of Process Migration.
Aric D. Blumer, Henning S. Mortveit, Cameron D. Patterson
2007GENDIV - A Hardware Algorithm for Intron and Exon String Detection in DNA Chains.
Octavian Cret, Zsolt Mathe, Paul Ciobanu, Sonia Marginean, Cristian Lelutiu
2007H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture.
Mahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker
2007H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture.
Adam Major, Ioannis Nousias, Sami Khawam, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan
2007HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation.
Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis
2007Hardware/Software Process Migration and RTL Simulation.
Aric D. Blumer, Cameron D. Patterson
2007High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA.
Tomas Dedek, Tomas Marek, Tomás Martínek
2007High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs.
José M. Claver, Germán León
2007High speed tablation system using an FPGA designed for distribution tables of frequent DNA subsequences.
Yoshiki Yamaguchi, Tsutomu Maruyama, Fumikazu Konishi, Akihiko Konagaya
2007Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C.
Jim Stevens
2007Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 Primitive.
Irwin O. Kennedy
2007Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core.
Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molderink, Pascal T. Wolkotte, Gerard J. M. Smit
2007Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs.
Katarina Paulsson, Michael Hübner, Günther Auer, Michael Dreschmann, Jürgen Becker
2007Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine.
Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell
2007Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms.
Roberto Gutiérrez, Javier Valls
2007Improving Annealing Via Directed Moves.
Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene, Doris T. Chen
2007Improving External Memory Access for Avalon Systems on Programmable Chips..
Hendrik Eeckhaut, Mark Christiaens, Dirk Stroobandt
2007Improving Pipelined Soft Processors with Multithreading.
Martin Labrecque, J. Gregory Steffan
2007Improving Timing-Driven FPGA Packing With Physical Information.
Doris T. Chen, Kristofer Vorwerk, Andrew A. Kennings
2007Incremental Fault Emulation.
Jan Torben Weinkopf, Klaus Harbich, Erich Barke
2007Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.
Encarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz
2007L4: An FPGA-Based Accelerator for Detailed Maze Routing.
John A. Nestor, Jeremy Lavine
2007Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices.
Rashad S. Oreifej, Rawad N. Al-Haddad, Heng Tan, Ronald F. DeMara
2007MORPHEUS: Heterogeneous Reconfigurable Computing.
Florian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker
2007Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance.
Micha Nelissen, Kees van Berkel, Sergei Sawitzki
2007Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors.
Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir
2007Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices.
Shannon Koh, Oliver Diessel
2007Monte Carlo Logarithmic Number System for Model Predictive Control.
Panagiotis D. Vouzis, Caroline Collange, Mark G. Arnold, Mayuresh V. Kothare
2007Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA.
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal
2007Multiplexer-based routing fabric for reconfigurable logic.
Martijn T. Bennebroek, Alexander Danilin
2007NoC Implementation in FPGA Using Torus Topology.
Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat
2007Novel Multi-Layer floorplanning for Heterogeneous FPGAs.
Love Singhal, Elaheh Bozorgzadeh
2007On the feasibility of early routing capacitance estimation for FPGAs.
Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung
2007On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project.
Katarina Paulsson, Michael Hübner, Jürgen Becker, Jean-Marc Philippe, Christian Gamrat
2007Performance Modeling of 2D Cellular Automata on FPGA.
S. Murtaza, Alfons G. Hoekstra, Peter M. A. Sloot
2007Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection.
Jorge Guajardo, Sandeep S. Kumar, Geert Jan Schrijen, Pim Tuyls
2007Power Reduction in Network Equipment through Adaptive Partial Reconfiguration.
Juanjo Noguera, Irwin O. Kennedy
2007Pre-route Interconnect Capacitance and Power Estimation in FPGAs.
Shilpa Bhoj, Dinesh Bhatia
2007RAMP Blue: A Message-Passing Manycore System in FPGAs.
Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg Gibeling, Pierre-Yves Droz
2007REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.
A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2007RIC Fast Adder and its Set Tolerant Implementation in FPGAs.
Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel
2007RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor.
Zdenek Pohl, Milan Tichý
2007ReconOS: An RTOS supporting Hard- and Software Threads.
Enno Lübbers, Marco Platzner
2007Redefining the FPGA for the Next Generation.
Steve Trimberger
2007Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems.
Mário P. Véstias, Horácio C. Neto
2007Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro.
Stefan Raaijmakers, Stephan Wong
2007Self-Healing Circuits for Space-Applications.
Thomas Panhofer, Martin Delvai
2007SoPC architecture for a Key Point Detector.
Harding Djakou Chati, Felix Mühlbauer, Tim Braun, Christophe Bobda, Karsten Berns
2007Soft IP core implementation of recursive least squares filter using only multplicative and additive operators.
Gaye Lightbody, Roger F. Woods, Jonathan Francey
2007Soft-Hard 3D FD-TD Solver for Non Destructive Evaluation.
Fernando Pardo, Paula López, Diego Cabello
2007Solving RC5 Challenges with Hardware -- a Distributed.net Perspective --.
Guerric Meurice de Dormale, John Bass, Jean-Jacques Quisquater
2007Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs.
Satish Sivaswamy, Kia Bazargan
2007Supporting High Level Language Semantics Within Hardware Resident Threads.
Erik K. Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David Andrews
2007System-Level Design for FPGAs.
Mark Dickinson
2007System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems.
Ali Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan
2007TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms.
Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun
2007The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems.
Andreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm, Markus Damm, Jan Haase, Florian Brame, Fernando Herrera, Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, Marcos Martínez
2007The Design of Multitasking Based Applications on Reconfigurable Instruction Cell Bsed Architectures.
Wei Han, Ioannis Nousias, Mark Muir, Tughrul Arslan, Ahmet T. Erdogan
2007The Intel Geneseo Project.
Ajay V. Bhatt
2007Time Predictable CPU and DMA Shared Memory Access.
Christof Pitter, Martin Schoeberl
2007VPH - A Tool for Exploring Hybrid FPGAs.
Chi Wai Yu
2007Virtualization on the Tartan Reconfigurable Architecture.
Mahim Mishra, Seth Copen Goldstein
2007Wirelength Prediction for FPGAs.
Audip Pandit, Ali Akoglu
2007Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing.
Peter M. Athanas, John W. Bowen, T. Dunham, Cameron D. Patterson, J. Rice, Matthew Shelburne, Jorge Surís, Mark B. Bucciero, Jonathan Graf
2007artNoC - A Novel Multi-Functional Router Architecture for Organic Computing.
Christian Schuck, Stefan Lamparth, Jürgen Becker