FPL B

183 papers

YearTitle / Authors
2006A Biologically Inspired FPGA Based Implementation of a Tactile Sensory System for Object Recognition and Texture Discrimination.
Martin J. Pearson, Mokhtar Nibouche, Anthony G. Pipe, Chris Melhuish, Ian Gilhespy, Benjamin Mitchinson, Kevin N. Gurney, Tony J. Prescott, Peter Redgrave
2006A Codesign Tool for High Level Systhesis of Vision Models on FPL.
Antonio Martínez-Álvarez, Leonardo Maria Reyneri, Francisco J. Pelayo, Christian A. Morillas, Samuel F. Romero
2006A Compiler Intermediate Representation for Reconfigurable Fabrics.
Zhi Guo, Walid A. Najjar
2006A Congestion Driven Placement Algorithm for FPGA Synthesis.
Yue Zhuo, Hao Li, Saraju P. Mohanty
2006A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors.
Hideharu Amano, Yohei Hasegawa, Shohei Abe, Kenichiro Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura
2006A Dual Cache for Performance and Energy Aware Reconfigurable HW.
Elena Perez Ramo, Javier Resano
2006A Dynamic Reconfigurable Fabric for Platform SoCs.
Christos A. Papachristou, J. Weaver, R. Vijayakumar, Francis G. Wolff
2006A Dynamically Reconfigurable Queue Scheduler.
Christoforos Kachris, Stamatis Vassiliadis
2006A Flexible Implementation of a Temporal Filter with Motion Compensation.
Thomas Perschke
2006A Framework for a Dynamically Reconfigurable System in a Parallel Multi-Tasking Environment.
Pil Woo Chun, Lev Kirischian
2006A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation.
Mário P. Véstias, Horácio C. Neto
2006A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes.
Paul Saunders, Anthony D. Fagan
2006A Layer Model for Systematically Designing Dynamically Reconfigurable Systems.
Boris Kettelhoit, Mario Porrmann
2006A Leak Resistant Architecture Against Side Channel Attacks.
Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Jean-Claude Bajard, Fernando Gehm Moraes
2006A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection.
Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi
2006A Multi-Context Pipelined Array for Embedded Systems.
Andrea Lodi, Claudio Mucci, Massimo Bocchi, Andrea Cappelli, Mario de Dominicis, Luca Ciccarelli
2006A Novel FPGA Design Acceleration Methodology Supported by a Unique RP Platform for Fast and Easy System Develpoment.
Carsten Bieser
2006A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design.
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2006A Novel Partial Bitstream Merging Methodology Accelerating Xilinx Virtex-II FPGA Based RP System Setup.
Carsten Bieser, Martin Bahlinger, Matthias Heinz, Christian Stops, Klaus D. Müller-Glaser
2006A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor.
Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani
2006A Reconfigurable Viterbi Decoder for a Communication Platform.
Imran Ahmed, Tughrul Arslan
2006A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory.
Minoru Watanabe, Fuminori Kobayashi
2006A Scalable Architecture for RSA Cryptography on Large FPGAs.
Allen Michalski, Duncan A. Buell
2006A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access.
Koen Van Renterghem, Dieter Verhulst, S. Verschuere, Pieter Demuytere, Jan Vandewege, Xing-Zhi Qiu
2006A Segmentation Model for Partial Run-Time Reconfiguration.
Mohamed Taher, Tarek A. El-Ghazawi
2006A Simulation Platform for Reconfigurable Computing Research.
Wenyin Fu, Katherine Compton
2006A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.
Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
2006A Thermal Management and Profiling Method for Reconfigurable Hardware Applications.
Phillip H. Jones, John W. Lockwood, Young H. Cho
2006A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.
Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera
2006A-B Nodes Classification for Power Estimation.
Elias Todorovich, Eduardo I. Boemo
2006Academia to IPO - A Modern Odyssey.
Ian Page
2006Activity Estimation for Field-Programmable Gate Arrays.
Julien Lamoureux, Steven J. E. Wilton
2006Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed.
Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou
2006Adaptive FPGAs: High-Level Architecture and a Synthesis Method.
Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
2006Adaptive Optics Real-Time Control Using FPGA.
Luis F. Rodríguez-Ramos, Angel Alonso, Fernando Gago, Jose V. Gigante, Guillermo Herrera, Teodora Viera
2006An Alternative to Sequential Architectures to Improve the Processing Time of Passive Stereovision Algorithms.
Abdelelah Naoulou, Jean-Louis Boizard, Jean-Yves Fourniols, Michel Devy
2006An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures.
Sajid Baloch, Tughrul Arslan, Adrian Stoica
2006An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems.
Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
2006An FPGA Implementation of K-Means Clustering for Color Images Based on Kd-Tree.
Takashi Saegusa, Tsutomu Maruyama
2006An FPGA Implementation of Pattern-Selective Pyramidal Image Fusion.
Oliver Sims, James Irvine
2006An FPGA Solver for Large SAT Problems.
Kenji Kanazawa, Tsutomu Maruyama
2006An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization.
Mateusz Majer
2006An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic.
C. K. Wong, Philip Heng Wai Leong
2006An FPGA-Based System on Chip for the Measurement of QCM Sensors Resolution.
María José Moure, María Dolores Valdés, Pablo Rodiz, Loreto Rodríguez-Pardo, José Fariña Rodríguez
2006An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor.
Miwa Miyata, Hideyuki Tsuchiya, Yuichiro Shibata, Kiyoshi Oguri
2006Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique.
Tom Van Court, Martin C. Herbordt
2006Applying Partial Reconfiguration to Networks-On-Chips.
Thilo Pionteck, Roman Koch, Carsten Albrecht
2006Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs.
Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert
2006Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays.
Florian Stock, Andreas Koch
2006Architecture and CAD for FPGA Clock Networks.
Julien Lamoureux, Steven J. E. Wilton
2006Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming.
Andreas Fidjeland, Wayne Luk
2006Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware.
Arfan Ghani, T. Martin McGinnity, Liam P. Maguire, Jim Harkin
2006Area-Efficient Implementation of a Pulse-Mode Neuron Model.
César Torres-Huitzil
2006Astra: An Advanced Space-Time Reconfigurable Architecture.
Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki
2006Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs.
Francisco-Javier Veredas, Hans-Jörg Pfleiderer
2006Automation of IP Core Interface Generation for Reconfigurable Computing.
Zhi Guo, Abhishek Mitra, Walid A. Najjar
2006Can Graphics Processing Units be Used to Improve Video Processing Systems?
Ben Cope
2006Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description.
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann, Oliver Pell
2006Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information.
Oliver Pell, Wayne Luk
2006Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures.
Fredy Rivera, Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Nader Bagherzadeh
2006Configware Design Space Exploration Using Rewriting Logic.
Carlos Morra
2006DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot.
Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe
2006Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm.
Konstantinos Masselos, George A. Constantinides, Qiang Liu
2006Defect-Tolerant FPGA Architecture Exploration.
Pongstorn Maidee, Kia Bazargan
2006Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver.
Angel Fernandez Herrero, Alberto Jimenez-Pacheco, Gabriel Caffarena, Javier Casajús-Quirós
2006Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit.
Pedro C. Diniz, Gokul Govindu
2006Detection Module in a Complementary Set of Sequences-Based Pulse Compression System.
Fernando J. Álvarez, Álvaro Hernández, Jesús Ureña, Juan Jesús García, Ana Jiménez, P. Santa Teresa
2006Development of IP Modules of Fuzzy Controllers for the Design of Embedded Systems on FPGAs.
María Brox, Santiago Sánchez-Solano
2006Dynamic Memory Sub-System for Reconfigurable Platforms.
Su-Shin Ang, George A. Constantinides
2006Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips.
Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
2006Efficient Cell Designs for Systolic Smith-Waterman Implementations.
Mustafa Gök, Çaglar Yilmaz
2006Efficient Realtime FPGA Implementation of the Trace Transform.
Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk
2006Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture.
Sujan Pandey, Manfred Glesner
2006Evaluation and Design of Processor-Like Reconfigurable Architectures.
Tobias Oppold
2006Executing Hardware Tasks on Dynamically Reconfigurable Devices Under Real-Time Conditions.
Klaus Danne, Roland Mühlenbernd, Marco Platzner
2006Executing Hardware as Parallel Software for Picoblaze Networks.
Pengyuan Yu, Patrick Schaumont
2006Execution Objects for Dynamically Reconfigurable FPGA Systems.
Timothy F. Oliver, Douglas L. Maskell
2006FPGA Architecture Design Methodology.
Mike Hutton
2006FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach.
Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong
2006FPGA Based Architectures for H. 264/AVC Video Compression Standard.
Luciano Volcan Agostini, Sergio Bampi
2006FPGA Based Imaging Particle Detector Trigger System.
Gustavo Martinez, Jesus Marin, Carlos Willmott
2006FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems.
Luis G. Barbero, John S. Thompson
2006FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.
Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin
2006FPGA Implementation and Power Modelling of the Fast Walsh Transform.
Shrutisagar Chandrasekaran, Abbes Amira
2006FPGA Implementation of 3-D Thermal Model Simulator.
Fernando Pardo, Paula López, Diego Cabello, Marco Balsi
2006FPGA Implementation of High-Performance PHM / DPHM Schedulers.
Enrique Soto, Elena Lago, Juan J. Rodríguez-Andina
2006FPGA Implementation of a Change-Driven Image Processing Architecture for Optical Flow Computation.
Julio C. Sosa, Rocío Gómez-Fabela, Jose Antonio Boluda, Fernando Pardo
2006FPGA Implementation of a Ridge Extraction Fingerprint Algorithm Based on Microblaze and Hardware Coprocessor.
Mariano López-García, Enrique F. Cantó-Navarro
2006FPGA Implementation of an Efficient Correlator for Complementary Sets of Sequences.
María del Carmen Pérez, Jesús Ureña, Álvaro Hernández, Carlos De Marziani, Alberto Ochoa, William P. Marnane
2006FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks.
François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater
2006FPGA Performance Optimization Via Chipwise Placement Considering Process Variations.
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
2006FPGA Vendor Agnostic True Random Number Generator.
Dries Schellekens, Bart Preneel, Ingrid Verbauwhede
2006FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex.
Christos-Savvas Bouganis, Peter Y. K. Cheung, Zhaoping Li
2006FPGA-Based Boundary-Scan Bist.
Ángel Quirós-Olozábal, Ma de los Ángeles Cifredo Chacón, Diego Gomez Vela
2006FPGAs at 65NM and Beyond - Powerful New FPGAs Bring New Challenges.
Ken McElvain
2006Fast Emulation of Permanent Faults in VLSI Systems.
David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil
2006Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA.
Joaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2006Fault Tolerant Reconfigurable Device Based on Autonomous-Repair Cells.
Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
2006Fpga-Oriented Secure Data Path Design: Implementation of a Public Key Coprocessor.
Nele Mentens, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede, Bart Preneel
2006From Equation to VHDL: Using Rewriting Logic for Automated Function Generation.
Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein
2006General Digit Width Normal Basis Multipliers with Circular and Linear Structure.
Martin Novotný, Jan Schmidt
2006High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD.
Owen Callanan, David Gregg, Andy Nisbet, Mike Peardon
2006High Speed Document Clustering in Reconfigurable Hardware.
G. Adam Covington, Charles L. G. Comstock, Andrew A. Levine, John W. Lockwood, Young H. Cho
2006High Speed High Fidelity Infrared Scene Simulation Using Reconfigurable Computing.
Vinay Sriram, David Kearney
2006High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures.
Rafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez
2006High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic.
Jonathan A. Clarke, George A. Constantinides
2006High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs.
Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
2006High-Performance and Parameterized Matrix Factorization on FPGAs.
Ling Zhuo, Viktor K. Prasanna
2006Hthreads: A Computational Model for Reconfigurable Devices.
Wesley Peck, Erik K. Anderson, Jason Agron, Jim Stevens, Fabrice Baijot, David Andrews
2006IPP Watermarking Technique for IP Core Protection on FPL Devices.
Encarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse
2006Identifying FPGA IP-Cores Based on Lookup Table Content Analysis.
Daniel Ziener, Stefan Assmus, Jürgen Teich
2006Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector Problem.
Ignacio Bravo Muñoz, Pedro Jiménez, Manuel Mazo, José Luis Lázaro, Alfredo Gardel Vicente
2006Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices.
James Moscola, Young H. Cho, John W. Lockwood
2006Implementation of a Parallel and Pipelined Watershed Algorithm on FPGA.
Dang Ba Khac Trieu, Tsutomu Maruyama
2006Improved Interpolation and System Integration for FPGA-Based Molecular Dynamics Simulations.
Yongfeng Gu, Tom Van Court, Martin C. Herbordt
2006Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support.
Hayden Kwok-Hay So, Robert W. Brodersen
2006Integrating the Electronics of the Control-Loops of the JPL/Boeing Gyroscope Within an Evolvable Hardware Architecture.
Evangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson
2006Intelligent Parking System Design Using FPGA.
Keith Gowan, Jason Nery, Henrick Han, Tony Sheng, Howard Li, Fakhreddine Karray, Insop Song
2006Investigating Trace Transform Architectures for Face Authentication.
Suhaib A. Fahmy
2006Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs.
Patrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan Bridgford
2006Mapping Recursive Functions to Reconfigurable Hardware.
George Ferizis, Hossam A. ElGindy
2006Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures.
Nastaran Baradaran, Pedro C. Diniz
2006Micro-Coded Datapaths: Populating the Space Between Finite State Machine and Processor.
Chidamber Kulkarni, Gordon J. Brebner
2006Minimizing Communication Cost for Reconfigurable Slot Modules.
Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich
2006Modular Partitioning for Incremental Compilation.
Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry P. Borer
2006Multi Stream Cipher Architecture for Reconfigurable System-on-Chip.
Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann, John A. Williams
2006Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics.
Michael T. Frederick, Arun K. Somani
2006Multi-layer Floorplanning on a Sequence of Reconfigurable Designs.
Love Singhal, Elaheh Bozorgzadeh
2006Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip.
Balasubramanian Sethuraman, Ranga Vemuri
2006Multitasking Support for Dynamically Reconfig Urable Systems.
Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner
2006Non-Uniform Random Number Generation Through Piecewise Linear Approximations.
David B. Thomas, Wayne Luk
2006Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip.
Balasubramanian Sethuraman
2006OSSS+R: Modelling and Simulating Self-Reconfigurable Systems.
Andreas Schallenberg, Wolfgang Nebel, Frank Oppenheimer
2006On Buffer Management Strategies for High Performance Computing with Reconfigurable Hardware.
Guillermo Marcus Martinez, Gerhard Lienhart, Andreas Kugel, Reinhard Männer
2006On Feasibility of FPGA Bitstream Compression During Placement and Routing.
Piotr Stepien, Milan Vasilko
2006On Reconfigurable Architectures for Efficient Matrix Inversion.
Goncalo M. de Matos, Horácio C. Neto
2006On-FPGA Communication Architectures and Design Factors.
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2006On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips.
Heikki Kariniemi, Jari Nurmi
2006Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures.
Janina A. Brenner, Jan van der Veen, Sándor P. Fekete, Julio A. de Oliveira Filho, Wolfgang Rosenstiel
2006Parsifal: A Generic and Configurable Fault Emulation Environment with Non-Classical Fault Models.
Jan Torben Weinkopf, Klaus Harbich, Erich Barke
2006Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign.
Marco D. Santambrogio, Donatella Sciuto
2006Perfecto: A Systemc-Based Performance Evaluation Framework for Dynamically Partially Reconfigurable Systems.
Pao-Ann Hsiung, Chun-Hsian Huang, Chih-Feng Liao
2006Performance Evaluation of a Preloading Model in Dynamically Reconfigurable Processors.
Kyprianos Papademetriou, Apostolos Dollas
2006Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip.
Yasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
2006Placement and Timing for FPGAs Considering Variations.
Mike Hutton, Yan Lin, Lei He
2006Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks.
Thilo Streichert
2006Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays.
Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton
2006Power Optimization Techniques for SRAM-Based FPGAs.
Somsubhra Mondal, Seda Ogrenci Memik
2006Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling.
Shrutisagar Chandrasekaran, Abbes Amira
2006Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators.
Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas
2006Predictive Load Balancing for Interconnected FPGAs.
Jason D. Bakos, Charles L. Cathey, Allen Michalski
2006Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006
2006Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools.
Xin Wang, Tapani Ahonen, Jari Nurmi
2006RAID 6 Hardware Acceleration.
Michael P. Gilroy, James Irvine
2006Rapid System-on-a-Programmable-Chip Development and Hardware Acceleration Of ANSI C Functions.
David J. Lau, Orion Pritchard
2006Ray Tracing Hardware System Using Plane-Sphere Intersections.
Yoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu, Ken-Ichi Suzuki, Tadao Nakamura, Nobuyuki Ohba
2006Real-Time Video Pixel Matching.
Jean-Baptiste Note, Mark Shand, Jean Vuillemin
2006Reconfigurable Architectures for Curve-Based Cryptography on Embedded Micro-Controllers.
Lejla Batina, Alireza Hodjat, David Hwang, Kazuo Sakiyama, Ingrid Verbauwhede
2006Reconfigurable Systems Enabled by a Network-on-Chip.
Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes
2006Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs.
Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2006Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding.
Allan Carroll, Carl Ebeling
2006Regular Expression Software Deceleration for Intrusion Detection Systems.
Zachary K. Baker, Viktor K. Prasanna, Hong-Jip Jung
2006Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA.
Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen
2006Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration.
Yohei Hori, Hiroyuki Yokoyama, Kenji Toda
2006Self-Reconfigurable Pervasive Platform for Cryptographic Application.
Arnaud Lagger, Andres Upegui, Eduardo Sanchez, Iván González
2006Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools.
David Grant, Scott Chin, Guy G. Lemieux
2006Shift-Or Circuit for Efficient Network Intrusion Detection Pattern Matching.
Huang-Chun Roan, Wen-Jyi Hwang, Chia-Tien Dan Lo
2006Sizing of Processing Arrays for FPGA-Based Computation.
Tom Van Court, Martin C. Herbordt
2006Skin Color Detection for Real Time Mobile Applications.
F. Javier Toledo, J. Javier Martínez, F. Javier Garrigós, José M. Ferrández, V. Rodellar
2006Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor.
K. S. Tham, Douglas L. Maskell
2006Synthesis of Analog Filters on a Continuous-Time FPAA Using a Genetic Algorithm.
Joachim Becker, Yiannos Manoli
2006Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem.
Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud
2006System Level Architecture Exploration for Reconfigurable Systems On Chip.
Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikolaos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo
2006TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs.
Manuel Saldaña, Paul Chow
2006The Darpa Multiple Precision Arithmetic Benchmark on a Reconfigurable Computer.
Cao Zhang, Duncan A. Buell, Allen Michalski
2006The Entropy of FPGA Reconfiguration.
Usama Malik, Oliver Diessel
2006Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System.
Sutjipto Arifin, Peter Y. K. Cheung
2006Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications.
Peter Alfke
2006Using Reconfigurable HW for High Dimensional CAF Computation.
Antonin Hermanek, Michal Kunes, Michal Kvasnicka
2006Variable-Length Hashing for Exact Pattern Matching.
Dionisios N. Pnevmatikatos, Aggelos Arelakis
2006Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor.
Oswaldo Cadenas, Graham M. Megson
2006Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems.
Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly
2006Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures.
Kostas Siozios, Dimitrios Soudris