FPL B

149 papers

YearTitle / Authors
2005A 11 GHz FPGA with Test Applications.
Chao You, Jong-Ru Guo, Michael Chu, Russell P. Kraft, Bryan S. Goda, John F. McDonald
2005A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs.
Usama Malik, Oliver Diessel
2005A Dynamically Reconfigurable Bluetooth Base Band Unit.
John Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang
2005A Flexible Circuit-Switched NOC for FPGA-Based Systems.
Clint Hilton, Brent E. Nelson
2005A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA.
Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano
2005A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata.
Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner
2005A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.
Klaus Danne, Marco Platzner
2005A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding.
Sinan Yalcin, Hasan F. Ates, Ilker Hamzaoglu
2005A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits.
Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves
2005A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow.
Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis
2005A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation.
Xin Jia, Ranga Vemuri
2005A Novel Toolset for the Development of FPGA-like Reconfigurable Logic.
Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki
2005A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC.
Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko Hännikäinen, Timo D. Hämäläinen
2005A Power-Performance Scalable FPGA Using Configurable Voltage Domains and Design Mapping Tool.
Frank Honoré
2005A Programmable Logic Architecture for Prototyping Clockless Circuits.
Laurent Fesquet, Marc Renaudin
2005A Reconfigurable Instruction Memory Hierarchy for Embedded Systems.
Zhiguo Ge, Hock-Beng Lim, Weng-Fai Wong
2005A Reconfigurable Perfect-Hashing Scheme for Packet Inspection.
Ioannis Sourdis, Dionisios N. Pnevmatikatos, Stephan Wong, Stamatis Vassiliadis
2005A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test.
Rawat Siripokarpirom
2005A Verilog RTL Synthesis Tool for Heterogeneous FPGAs.
Peter Jamieson, Jonathan Rose
2005Accelerating Molecular Dynamics Simulations With Configurable Circuits.
Yongfeng Gu, Tom Van Court, Martin C. Herbordt
2005Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems.
Najeem Lawal, Benny Thörnberg, Mattias O'Nils
2005An Analytical Approach to Generation and Exploration of Reconfigurable Architectures.
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2005An Approach to Scalable Molecular Dynamics Simulation Using Supercomputing Adaptive Processing Elements.
Luis E. Cordova, Duncan A. Buell
2005An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation.
Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
2005An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications.
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
2005An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning.
Pedro M. Domingos, Fernando M. Silva, Horácio C. Neto
2005An Emulation Model for Sequential ATPG-Based Bounded Model Checking.
Qiang Qiang, Daniel G. Saab, Jacob A. Abraham
2005An FPGA Application with High Speed Serial Transceiver Running at Sub-nominal Rate.
Dusan Suvakovic, Ilija Hadzic
2005An FPGA Network Architecture for Accelerating 3DES - CBC.
Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann
2005An FPGA Solver for WSAT Algorithms.
Kenji Kanazawa, Tsutomu Maruyama
2005An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding.
Kaushik Ravindran, Nadathur Satish, Yujia Jin, Kurt Keutzer
2005An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration?
Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa
2005An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform.
Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis
2005Applying the Small-World Network to Routing Structure of FPGAs.
Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi
2005Architecture-Adaptive Routability-Driven Placement for FPGAs.
Akshay Sharma, Carl Ebeling, Scott Hauck
2005Area-Efficient 2-D Shift-Variant Convolvers for FPGA-based Digital Image Processing.
Francisco Cardells-Tormo, Pep-Lluis Molinet, Jordi Sempere-Agulló, Luis Baldez, Marc Bautista-Palacios
2005Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC.
Mark Holland, Scott Hauck
2005Bitwise Optimised CAM for Network Intrusion Detection Systems.
Sherif Yusuf, Wayne Luk
2005CPU-independent Assembler in an FPGA.
Georg Acher, Rainer Buchty, Carsten Trinitis
2005CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools.
Robert G. Dimond, Oskar Mencer, Wayne Luk
2005Cluster Architecture for Reconfigurable Signal Processing Engine for Wireless Communication.
Miyoshi Saito, Hisanori Fujisawa, Nobuo Ujiie, Hideki Yoshizawa
2005Communication Synthesis in a multiprocessor environment.
Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
2005Compilation and Management of Phase-Optimized Reconfigurable Systems.
Henry Styles, Wayne Luk
2005Computer Arithmetic Synthesis Technologies on Reconfigurable Platforms.
Kuen Hung Tsoi
2005Configurable Hardware/Software Architecture for Data Acquisition: Implementation on FPGA.
Marc Bautista-Palacios, Luis Baldez, Jordi Sempere-Agulló, Atilà Herms-Berenguer, Francisco Cardells-Tormo, Pep-Lluis Molinet
2005Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis.
Michael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber
2005Configuration Merging for Adaptive Computer Applications.
Nico Kasprzyk, Jan van der Veen, Andreas Koch
2005Context Saving and Restoring for Multitasking in Reconfigurable Systems.
Heiko Kalte, Mario Porrmann
2005Coping With Uncertainty in FPGA Architecture Design.
Boris Ratchev, Mike Hutton, David Mendel
2005Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes.
Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei
2005Defect Tolerance in Multiple-FPGA Systems.
Zohair Hyder, John Wawrzynek
2005Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement.
Anthony J. Yu, Guy G. Lemieux
2005Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor.
Martin J. Pearson, Chris Melhuish, Anthony G. Pipe, Mokhtar Nibouche, Ian Gilhespy, Kevin N. Gurney, Benjamin Mitchinson
2005Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System.
Carlos Leong, P. Bento, Pedro Miguel Rodrigues, Andreia Trindade, José C. Silva, Pedro Lousã, Joel Rego, J. Nobre, João Varela, João Paulo Teixeira, Isabel C. Teixeira
2005Design of a Dynamic Reconfigurable Multi-Grained Hardware Architecture with Adaptive Runtime Routing.
Alexander Thomas
2005Dual FiXed-point : An Efficient Alternative to Floating-point Computation for DSP applications.
Chun Te Ewe
2005DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices.
Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs.
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, Dirk Timmermann
2005Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks.
Antonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz
2005Efficient Execution on Reconfigurable Devices Using Concepts of Pipelining.
Florian Dittmann
2005Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates.
Fabian Angarita, A. Perez-Pascual, T. Sansaloni, Javier Valls
2005Efficient Hardware Architectures for Modular Multiplication on FPGAs.
David Narh Amanor, Viktor Bunimov, Christof Paar, Jan Pelzl, Manfred Schimmler
2005Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA.
Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri
2005Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes.
Jawad Khan, Ranga Vemuri
2005Energy-Efficient NoC for Best-Effort Communication.
Pascal T. Wolkotte, Gerard J. M. Smit, Jens E. Becker
2005Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic.
Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
2005Evaluation Strategies for Coarse Grained Reconfigurable Architectures.
Hendrik Lange, Hartmut Schröder
2005Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures.
Tobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel, Urs Kanus, Wolfgang Straßer
2005Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor.
Chi-Wei Wang, Nicholas P. Carter, Richard B. Kujoth, Jeffrey J. Cook, Derek B. Gottlieb
2005Exploration of Heterogeneous Reconfigurable Architectures.
Alastair M. Smith
2005FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations.
Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein
2005FPGA Finite-Difference Time-Domain solver for thermal simulation.
Fernando Pardo, Paula López, Diego Cabello, Marco Balsi
2005FPGA Implementation of a GF(2
Maurice Keller, Tim Kerins, William P. Marnane
2005FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach.
J. Javier Martínez, F. Javier Toledo, F. Javier Garrigós, José Manuel Ferrández de Vicente
2005FPGA Implementation of an Augmented Reality Application for Visually Impaired People.
F. Javier Toledo, J. Javier Martínez, F. Javier Garrigós, José Manuel Ferrández de Vicente
2005FPGA Interconnect Fault tolerance.
Nicola Campregher
2005FPGA PLB Evaluation using Quantified Boolean Satisfiability.
Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2005FPGA's Middleware for Software Defined Radio Applications.
Xavier Revés, Vuk Marojevic, Ramon Ferrús, Antoni Gelonch
2005FPGA-Accelerated Reconstruction of Gene Regulatory Networks.
Iosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides
2005FPGA-Aware Garbage Collection in Java.
Philippe Faes, Mark Christiaens, Dries Buytaert, Dirk Stroobandt
2005FPGA-based implementation and comparison of recursive and iterative algorithms.
Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel
2005Fast FPGA Placement using Space-filling Curve.
Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy
2005Fault-Tolerant XGFT Network-On-Chip for Multi-Processor System-on-Chip Circuits.
Heikki Kariniemi, Jari Nurmi
2005Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration.
Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl
2005Finite Field Division Implementation.
Jean-Pierre Deschamps, Gustavo Sutter
2005GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips.
Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin
2005Generalizing Square Attack using Side-Channels of an AES Implementation on an FPGA.
Vincent Carlier, Hervé Chabanne, Emmanuelle Dottax, Hervé Pelletier
2005HAIL: A Hardware-Accelerated Algorithm for Language Identification.
Charles M. Kastner, G. Adam Covington, Andrew A. Levine, John W. Lockwood
2005Hardware Emulation of a Network on Chip Architecture based on a Clockwork Routed Manhattan Street Network.
Kurian Oommen, David Harle
2005Hashing + Memory = Low Cost, Exact Pattern Matching.
Giorgos Papadopoulos, Dionisios N. Pnevmatikatos
2005Heterogeneity Exploration for Multiple 2D Filter Designs.
Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides
2005Hierarchical Placement for Large-scale FPAA.
I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson
2005High Performance Stereo Computation Architecture.
Javier Díaz, Eduardo Ros, Sonia Mota, Eva M. Ortigosa, Begoña del Pino
2005High Speed / Low Power Architectures for the Finite Radon Transform.
Shrutisagar Chandrasekaran, Abbes Amira
2005High-Throughput Reconfigurable Computing: A Design Study of an IDEA Encryption Cryptosystem on the SRC-6e Reconfigurable Computer.
Allen Michalski, Kris Gaj, Duncan A. Buell
2005High-speed and Memory Efficient TCP Stream Scanning using FPGA.
Yutaka Sugawara, Mary Inaba, Kei Hiraki
2005Highly Automated FPGA Synthesis of Application-Specific Protocol Processors.
Seppo Virtanen, Dragos Truscan, Jani Paakkulainen, Jouni Isoaho, Johan Lilius
2005Implementation of Ranking Filters on General Purpose and Reconfigurable Architecture Based on High Density FPGA Devices.
Dragomir Milojevic
2005Instruction Set Extension Using Microblaze Processor.
János Lazányi
2005Integration of a NoC-Based Multimedia Processing Platform.
Tapani Ahonen, Jari Nurmi
2005LAMP: A Tool Suite for Families of FPGA-Based Application Accelerators.
Tom Van Court, Martin C. Herbordt
2005Leveraging Reconfigurability in the Design Process.
Lesley Shannon, Paul Chow
2005Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications.
Sajid Baloch, Imran Ahmed, Tughrul Arslan, Adrian Stoica
2005Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor.
Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello
2005MILP-based Placement and Routing for Dataflow Architecture.
Michael B. Healy, Mongkol Ekpanyapong, Sung Kyu Lim
2005Magnetic remanent memory structures for dynamically reconfigurable fine grain FPGA.
Nicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli
2005Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture.
Bingfeng Mei, Francisco-Javier Veredas, Bart Masschelein
2005Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks.
Andy Gean Ye, Jonathan Rose
2005MechanoProcessor: Modelling the Rodent Whisker Sensory System using FPGA.
Martin J. Pearson
2005Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs.
Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Paul R. Schumacher, Kees A. Vissers
2005Modular Partial Reconfiguration in Virtex FPGAs.
N. Pete Sedcole, Brandon Blodget, Tobias Becker, James Anderson, Patrick Lysaght
2005Mullet - A Parallel Multiplier Generator.
Kuen Hung Tsoi, Philip Heng Wai Leong
2005Multidimensional Dynamic Programming for Homology Search.
Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko Konagaya
2005Mutable Codesign for Embedded Protocol Processing.
Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely
2005NetFlow Probe Intended for High-Speed Networks.
Martin Zádník, Tomas Pecenka, Jan Korenek
2005Next Generation Architectures and CAD for Power Aware Programmable Fabrics.
Rajarshee P. Bharadwaj
2005Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing.
Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
2005On the Reliability Evaluation of SRAM-Based FPGA Designs.
Olivier Héron, Talal Arnaout, Hans-Joachim Wunderlich
2005On-Chip Communication Topology Synthesis for a Shared Memory Architecture.
Sujan Pandey, Manfred Glesner, Max Mühlhäuser
2005Optimization of Start-Up Time and Quiescent Power Consumption of FPGAs.
Artur Schiefer, Udo Kebschull
2005PAHLS: Towards Run-Time Synthesis for FPGAs.
Renqiu Huang, Ranga Vemuri
2005PGR: A Software Package for Reconfigurable Super-Computing.
Tsuyoshi Hamada, Naohito Nakasato
2005Parameterized Logic Power Consumption Models for FPGA based Systems.
Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides
2005Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs.
Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
2005Performance Tuning of Iterative Algorithms in Signal Processing.
Zdenek Pohl, Premysl Sucha, Jiri Kadlec, Zdenek Hanzálek
2005Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures.
Juanjo Noguera, Rosa M. Badia
2005Post-Placement BDD-Based Decomposition for FPGAs.
Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown
2005Power and Area Optimization for Multiple Restricted Multiplication.
Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
2005Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005
Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong
2005Programmable Numerical Function Generators: Architectures and Synthesis Method.
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
2005Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata.
Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner
2005QPF: Efficient Quadratic Placement for FPGAs.
Yonghong Xu, Mohammed A. S. Khalid
2005Real-Time Feature Extraction for High Speed Networks.
David Nguyen, Gokhan Memik, Seda Ogrenci Memik, Alok N. Choudhary
2005Real-time Generation of Three-Dimensional Motion Fields.
Hiroaki Niitsuma, Tsutomu Maruyama
2005Real-time Handel-C Based Implementation of DV Decoder.
Marek Gorgon, Slawomir Cichon, Miroslaw Pac
2005Reconfigurable Architectures for Real-Time Network Anomaly Detection.
David Nguyen
2005Requested-QoS Driven Runtime Reconfiguration of Mobile Devices.
Hiren Joshi, S. S. Verma, G. K. Sharma
2005Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors.
Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon
2005Safe PLD-based Programmable Controllers.
Jacobo Álvarez, Jorge Marcos, Santiago Fernández
2005Snort Offloader: A Reconfigurable Hardware NIDS Filter.
Haoyu Song, Todd S. Sproull, Michael Attig, John W. Lockwood
2005Snow 2.0 IP Core for Trusted Hardware.
Wenhai Fang, Thomas Johansson, Lambert Spaanenburg
2005Statistical Power Estimation for FPGA.
Elias Todorovich, Fabian Angarita, Javier Valls, Eduardo I. Boemo
2005Testing Superscalar Processors in Functional Mode.
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
2005Timing Aware Interconnect Prediction Models for FPGAs.
Shankar Balachandran, Dinesh Bhatia
2005Towards a Reconfigurable Tracking System.
Sebastien C. Wong, Mark Jasiunas, David A. Kearney
2005Trident: An FPGA Compiler Framework for Floating-Point Algorithms.
Justin L. Tripp, Kristopher D. Peterson, Christine Ahrens, Jeffrey D. Poznanovic, Maya B. Gokhale
2005Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow.
Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung
2005Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes.
Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2005Ziggurat-based Hardware Gaussian Random Number Generator.
Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk