FPL B

102 papers

YearTitle / Authors
2000A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System.
Stephen J. Bellis, William P. Marnane
2000A Co-processor System with a Virtex FPGA for Evolutionary Computation.
Yoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu Hoshino
2000A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems.
Xue-Jie Zhang, Kam-Wing Ng, Wayne Luk
2000A Comparison of FPGA Implementations of Bit-Level and Word-Level Matrix Multipliers.
Radhika S. Grover, Weijia Shang, Qiang Li
2000A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors.
Xinan Tang, Manning Aalsma, Raymond Jou
2000A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization.
Johan Ditmar, Kjell Torkelsson, Axel Jantsch
2000A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs.
Tero Rissa, Jarkko Niittylahti
2000A Mapping Methodology for Code Trees onto LUT-Based FPGAs.
Holger Kropp, Carsten Reuter
2000A Multi-node Dynamic Reconfigurable Computing System with Distributed Reconfiguration Controller.
Abdellah Touhafi
2000A New Floorplanning Method for FPGA Architectural Research.
Frank Wolz, Reiner Kolla
2000A Parallel Pipelined SAT Solver for FPGAs.
Mark Redekopp, Andreas Dandalis
2000A Placement Algorithm for FPGA Designs with Multiple I/O Standards.
Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman
2000A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor.
André Brinkmann, Dominik Langen, Ulrich Rückert
2000A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems.
Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano
2000A Self-Reconfigurable Gate Array Architecture.
Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro Mei, Viktor K. Prasanna
2000A Specific Test Methodology for Symmetric SRAM-Based FPGAs.
Michel Renovell
2000A Stream Processor Architecture Based on the Configurable CEPRA-S.
Rolf Hoffmann, Bernd Ulmann, Klaus-Peter Völkmann, Stefan Waldschmidt
2000A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology.
Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima
2000An FPFA Based Scheduling Coprocessor for Dynamic Priority Scheduling in Hard-Time Systems.
Jens Hildebrandt, Dirk Timmermann
2000An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture.
Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada
2000An Innovative Approach to Couple EDA Tools with Reconfigurable Hardware.
Uwe Hatnik, Jürgen Haufe, Peter Schwarz
2000Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform.
Javier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz
2000Area-Optimized Technology Mapping for Hybrid FPGAs.
Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier
2000Automatic Temporal Floorplanning with Guaranteed Solution Feasibility.
Milan Vasilko, Graham Benyon-Tinker
2000Balancing Logic Utilization and Area Efficiency in FPGAs.
Russell Tessier, Heather Giza
2000Behavioural Language Compilation with Virtual Hardware Management.
Oliver Diessel, George J. Milne
2000CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs.
Joerg Abke, Erich Barke
2000Combining Serialisation and Reconfiguration for FPGA Designs.
Arran Derbyshire, Wayne Luk
2000Compact Spiking Neural Network Implementation in FPGA.
Selene Maya, M. Rocio Reynoso, César Torres-Huitzil, Miguel O. Arias-Estrada
2000Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis.
Bernardo Kastrup, Jeroen Trum, Orlando Moreira, Jan Hoogerbrugge, Jef L. van Meerbergen
2000Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers.
Juanjo Noguera, Rosa M. Badia
2000DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications.
Jürgen Becker, Thilo Pionteck, Manfred Glesner
2000Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware.
Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano
2000Design Visualisation for Dynamically Reconfigurable Systems.
Milan Vasilko
2000Design and Implementation of an XC6216 FPGA Model in Verilog.
Alexander Glasmacher, Kai Woska
2000Design of a Fault Tolerant FPGA.
Thomas Bartzick, Michael Henze, Jens Kickler, Kai Woska
2000Educational Programmable Hardware Prototyping and Verification System.
Andrej Trost, Andrej Zemva, Baldomir Zajc
2000Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction.
Christophe Bobda, Thomas Lehmann
2000Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.
Sushil Chandra Jain, Anshul Kumar, Shashi Kumar
2000Efficient Self-Reconfigurable Implementations Using On-chip Memory.
Sameer Wadhwa, Andreas Dandalis
2000Evaluation of Accelerator Designs for Subgraph Isomorphism Problem.
Shuichi Ichikawa, Hidemitsu Saito, Lerdtanaseangtham Udorn, Kouji Konishi
2000Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs.
Andrzej Krasniewski
2000FPGA Implementation of a Prototype WDM On-Line Scheduler.
Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh
2000FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers.
Bogdan Matasaru, Tudor Jebelean
2000FPGA-Based Emulation: Industrial and Custom Prototyping Solutions.
Helena Krupnova, Gabriele Saucier
2000FPGA-Based Prototyping for Product Definition.
Rainer Kress, Andreas Pyttel, Alexander Sedlmeier
2000FPL Curriculum at Tallinn Technical University.
Kalle Tammemäe, T. Evartson
2000Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic.
Alfred Blaickner, O. Nagy, Herbert Grünbacher
2000Field Programmable Communication Emulation and Optimization for Embedded System Design.
Frank-Michael Renner, Jürgen Becker, Manfred Glesner
2000Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings
Reiner W. Hartenstein, Herbert Grünbacher
2000Formal Verification of a Reconfigurable Microprocessor.
Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube
2000From Reconfigurability to Evolution in Construction Systems: Spanning the Electronic, Microfluidic and Biomolecular Domains.
John S. McCaskill, Patrick Wagler
2000Generating Addresses for Multi-dimensional Array Access in FPGA On-chip Memory.
Andreas C. Döring, Gunther Lustig
2000Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures.
Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger
2000High Speed Computation of Lattice gas Automata with FPFA.
Tomoyoshi Kobori, Tsutomu Maruyama, Tsutomu Hoshino
2000High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs.
Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard Tröster
2000Implementation of Virtual Circuits by Means of the FIPSOC Devices.
E. Cantó, Juan Manuel Moreno, Joan Cabestany, Ignacio Lacadena, Josep Maria Insenser
2000Implementing Kak Neural Networks on a Reconfigurable Computing Platform.
Jihan Zhu, George J. Milne
2000Implementing a Fieldbus Interface Using an FPGA.
G. Lías, María Dolores Valdés, Miguel A. Domínguez, María José Moure
2000Internet Connected FPL.
Hamish Fallside, Michael John Sebastian Smith
2000It's FPL, Jim - But Not as We Know It! Opportunities for the New Commercial Architectures.
Tom Kean
2000Mapping of DSP Algorithms on Field Programmable Function Arrays.
Paul M. Heysters, Jaap Smit, Gerard J. M. Smit, Paul J. M. Havinga
2000Memory Access Schemes for Configurable Processors.
Holger Lange, Andreas Koch
2000Multifunctional Programmable Single-Board CAN Monitoring Module.
Petr Pfeifer
2000Multiple-Wordlength Resource Binding.
George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000Multiplexer Based Reconfiguration for Virtex Multipliers.
Tim Courtney, Richard H. Turner, Roger F. Woods
2000Multitasking on FPGA Coprocessors.
Harald Simmler, L. Levinson, Reinhard Männer
2000On Applying Software Development Best Practice to FPFAs in Safety Critical Systems.
A. Hilton, J. Hall
2000On Availability of Bit-Narrow Operations in General-Purpose Applications.
Darko Stefanovic, Margaret Martonosi
2000Optimization of Run-Time Reconfigurable Embedded Systems.
Michael Eisenring, Marco Platzner
2000Optimum Functional Decomposition for LUT-Based FPGA Synthesis.
Jian Qiao, Makoto Ikeda, Kunihiro Asada
2000Partial Run-Time Reconfiguration Using JRTR.
Scott McMillan, Steve Guccione
2000Performance Penalty for Fault Tolerance in Roving STARs.
John Marty Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici
2000Placement of Linear Arrays.
Erwan Fabiani, Dominique Lavenier
2000Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications.
Jim Tørresen
2000Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration.
Brandon Blodget
2000Programmable System Level Integration Brings System-on-Chip Design to the Desktop.
Guy Lecurieux Lafayette
2000Real-Time Face Detection on a Configurable Hardware System.
Rob McCready
2000Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling.
Christian Siemers
2000Reconfigurable Computing for Speech Recognition: Preliminary Findings.
Stephen J. Melnikoff, Philip James-Roxby, Steven F. Quigley, Martin J. Russell
2000Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits.
Marios Iliopoulos, Theodore Antonakopoulos
2000Reconfigurable Systems: New Activities in Asia.
Hideharu Amano, Yuichiro Shibata, Masaki Uno
2000Reusable DSP Functions in FPGAs.
Jernej Andrejas, Andrej Trost
2000Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic.
Hagen Ploog, Mathias Schmalisch, Dirk Timmermann
2000Self-Testing of Linear Segments in User-Programmed FPGAs.
Pawel Tomaszewicz
2000Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play?
Jan M. Rabaey
2000Software Radio Reconfigurable Hardware System (SHaRe).
Xavier Revés, Antoni Gelonch, Ferran Casadevall, José L. García
2000StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox.
Oskar Mencer, Heiko Hübert, Martin Morf, Michael J. Flynn
2000Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT.
Jörn Gause, Peter Y. K. Cheung, Wayne Luk
2000Stream Computations Organized for Reconfigurable Execution (SCORE).
Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon
2000Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs.
Valery Sklyarov
2000System Design with Genetic Algorithms.
Christine Bauer, Peter Zipf, Hans Wojtkowiak
2000Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer.
Hossam A. ElGindy, Martin Middendorf, Hartmut Schmeck, Bernd Schmidt
2000The Fastest Multiplier on FPGAs with Redundant Binary Representation.
Takahiro Miomo, Koichi Yasuoka, Masanori Kanazawa
2000The Implementation of Synchronous Dataflow Graphs Using Reconfigurable Hardware.
Martyn Edwards, Peter Green
2000The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing.
Jean-Michel Raczinski, Stéphane Sladek
2000The Rising Wave of Field Programmability.
Tsugio Makimoto
2000The Role of the Embedded Memories in the Implementation of Artificial Neural Networks.
Rafael Gadea Gironés, Vicente Herrero-Bosch, Angel Sebastiá, Antonio Mocholí Salcedo
2000Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS.
Sriram Govindarajan, Ranga Vemuri
2000Toward Uniform Approach to Design of Evolvable Hardware Based Systems.
Lukás Sekanina, Azeddien M. Sllame
2000Verification of Dynamically Reconfigurable Logic.
David Robinson, Patrick Lysaght
2000Wireless Base Station Design Using a Reconfigurable Communications Processor.
Chris Phillips