FPGA A

54 papers

YearTitle / Authors
2026A Cloud-Native FPGA-Accelerated Framework and Methodology for Hardware Verification.
Irfan Waheed, Wajahat Riaz, Babar Sohail
2026A Hierarchical Methodology for Hardware Design Comparison in HPC Workloads.
Doru-Thom Popovici, Mario Vega, Angelos Ioannou, Fabien Chaix, Dania Susanne Mosuli, Blair Reasoner, Tan Nguyen, Xiaokun Yang, John Shalf
2026A High-level Synthesis Toolchain for the Julia Language.
Benedict Short, Ian McInerney, John Wickerson
2026A Model-Hardware Co-design Framework for Robust and Efficient CNN-Based SAR ATR.
Sachini Wickramasinghe, Tian Ye, Cauligi S. Raghavendra, Viktor K. Prasanna
2026A2H-MAS: An Algorithm-to-HLS Multi-Agent System for Automated and Reliable FPGA Implementation.
Jie Lei, Ruofan Jia, J. Andrew Zhang, Hao Zhang
2026AI-Assisted Copilot Automation for Reliable FPGA Verification at Hyperscale.
Linh Nguyen, Nguyen Le, Tony-Dat Tran, Jagannath Panduranga Rao, Andrew Putnam
2026AgRefactor: Refactoring for HLS Compatibility with a Self-Evolving Agentic Workflow.
Yang Zou, Zijian Ding, Chi Wang, Yizhou Sun, Jason Cong
2026Analysis and Optimization of Input-Dependent Stream Processing Pipelines on FPGAs.
Shashank Obla, Bin Li, James C. Hoe
2026Attest Like Software: Formally-Verified Software-Programmable Proof of Execution Architecture Using SoC FPGAs.
Fatemeh Arkannezhad, Nader Sehatbakhsh
2026Bridging the Gap: A Module-Context Modeling Methodology for Hyperscale FPGA Applications.
Madison N. Emas, Austin Baylis, Greg Stitt
2026CAD-in-the-Cloud: Protecting FPGA Design Privacy via Redacted Netlists.
Eddie Rydell, Reilly McKendrick, Jeffrey Goeders
2026CODESCA: Co-Design for Spectral Clustering Acceleration.
Zhengyan Liu, Ce Guo, Zehuan Zhang, Qiang Liu, Wayne Luk
2026CXL-SpecKV: A Disaggregated FPGA Speculative KV-Cache for Datacenter LLM Serving.
Dong Liu, Yanxuan Yu
2026Chext: A Domain-specific Language for Safe and Agile Elastic Dataflow Accelerators.
Canberk Sönmez, Mohamed Shahawy, Paolo Ienne
2026Chrono-Fabric: A Decoupled Hierarchical Framework for Cycle-Accurate Coordination in Multi-FPGA Systems.
Congwu Zhang, Panyu Wang, Yazhou Wang, Bibo Yang, Mingyu Chen, Yungang Bao, Ke Zhang
2026Closing the Loop on FPGA Verification: An Iterative Framework for Maximizing Routing Resource Coverage.
Ruthwik Reddy Sunketa, Aman Arora
2026EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS.
Shun Katsumi, Emmet Murphy, Lana Josipovic
2026EdgeSort: A Sub-100 ns, Line-Rate FPGA Streaming Sorter.
Greg Stitt, Wesley Piard, Christopher Crary
2026Enabling Efficient SpMM for Sparse Attention on GEMM-Optimized Hardware with Block Aggregation.
Tianchu Ji, Niranjan Balasubramanian, Michael Ferdman, Peter A. Milder
2026Exploring Real-Time Power Electronics Simulation on AMD AIEs.
Shouyu Du, Zhenyu Xu, Miaoxiang Yu, Jillian Cai, Yeonho Jeong, Tao Wei
2026FARE: A Fine-grained Pipelined Reconfigurable FlashAttention Kernel.
Kaushikkumar S. Rathva, Aakarsh Alam, Srini Srinivasan, Sumit K. Mandal
2026Finding and Understanding Bugs in FPGA Place-and-Route Engines.
Ollie Cosgrove, Alastair F. Donaldson, John Wickerson
2026FlexMSM: A Flexible FPGA-Based Accelerator for Multi-Scalar Multiplication with Reconfigurable Modular Arithmetic and Optimized Pippenger Scheduling.
Cheng Chen, Gangqiang Yang, Hongchao Zhou, Hailiang Xiong, Zhiguo Wan
2026Gatling-V: An FPGA-based RISC-V Vector Core with Single-Issue, Multiple In-Flight Instruction Execution.
Farid Chalabi, Guy Lemieux
2026HACE: HLS-Tool-Agnostic CDFG Extraction from RTL Designs.
Carmine Rizzi, Sebastian Pfeiler, Lana Josipovic
2026HERA: A Bandwidth-efficient Accelerator for Fully Homomorphic Encryption on HBM-enabled FPGA.
Zhihan Xu, Rajgopal Kannan, Viktor K. Prasanna
2026HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV.
Shijie Liu, Zhenghao Zeng, Han Jiao, Yihua Huang
2026HGQ: High Granularity Quantization for Real-time Neural Networks on FPGAs.
Chang Sun, Zhiqiang Que, Thea Aarrestad, Vladimir Loncar, Jennifer Ngadiuba, Wayne Luk, Maria Spiropulu
2026Hardware Accelerated FPGA Divide-and-Conquer Page Placement in Milliseconds.
Ezra Thomas, Jing Li, André DeHon
2026Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures (FPGAs) for Edge and Physical AI.
Bin Xu, Ayan Banerjee, Sandeep K. S. Gupta
2026HiLFS: FPGA-Orchestrated File System for High-Level Synthesis.
YoungSeok Na, Linus Y. Wong, André DeHon, Jing Jane Li
2026Hummingbird+: Advancing FPGA-based LLM Deployment from Research Prototype to Edge Product.
Jindong Li, Tenglong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang, Yi Zeng
2026Hyperscale FPGA Engineering Systems at Microsoft.
Rob Rydberg, Madison N. Emas, John Demme, Ana Ibarra, Kara Kagi, Brandon Klouchek, Abhijeet Lawande, Todd Massengill, David J. Powers, Andrew Putnam
2026Improving Area Efficiency in Synthesizable eFPGA with Multi-output Logic Cell and Domain-Specific Routing Architecture.
Ryo Iwasaki, Tatsuya Sasaki, Yumi Iseki, Sota Kohata, Miyu Yoshida, Kenshu Seto, Masahiro Iida
2026KANELÉ: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation.
Duc Hoang, Aarush Gupta, Philip C. Harris
2026MARU: An ML-Based Framework for Area Estimation from FPGA Resource Usage.
Tarun Kholay, Anup Ashok Kedilaya, Aman Arora, Jaydeep P. Kulkarni, Lizy K. John
2026MegaTurbo: A Scalable FPGA-based Engine for MegaFlow Classifier in Open vSwitch.
Sheng Lan, Ying Li, Zhongxian Liang, Wenjun Li, Yao Xin, Ying Wan, Hui Li, Weizhe Zhang
2026Modulation Recognition in a System-on-Chip.
John Wohlbier, Daniel Bonness, Jodi Miller, Marika Schubert
2026Multi-Port Memory with Bidirectional Ports for FPGAs Using XOR and LVT Methods.
Kevin Townsend
2026NysX: An Accurate and Energy-Efficient FPGA Accelerator for Hyperdimensional Graph Classification at the Edge.
Jebacyril Arockiaraj, Dhruv Parikh, Viktor K. Prasanna
2026OpenPCIe: An Open-Source PCIe Controller.
Idris Somoye, David Jovel, Lamia Mannan
2026Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS.
Rouzbeh Pirayadi, Ayatallah Elakhras, Mirjana Stojilovic, Paolo Ienne
2026PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros.
Pravin Gaikwad, Aritra Dasgupta, Sudipta Paria, Peyman Dehghanzadeh, Jonathan Cruz, Swarup Bhunia
2026Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2026, Seaside, CA, USA, February 22-24, 2026
Jing Li, Grace Zgheib
2026RND: A Mixed-Grained Parallel Routing Framework with Region-based Net Decomposition for UltraScale FPGAs.
Wenhao Lin, Zewen Li, Xinshi Zang, Evangeline F. Y. Young
2026SORCERI: Streaming Overlay Acceleration for Highly Contracted Electron Repulsion Integral Computations in Quantum Chemistry.
Philip Stachura, Xin Wu, Christian Plessl, Zhenman Fang
2026Striking the Balance: GEMM Performance Optimization Across Generations of Ryzen™ AI NPUs.
Endri Taka, Andre Roesti, Joseph Melber, Pranathi Vasireddy, Kristof Denolf, Diana Marculescu
2026Synchronized CPU-FPGA Tracing for Heterogeneous Platforms.
Nicolas Deloumeau, Tarek Ould-Bachir, David Evans, Andrew Handke, Jamie Sanderson, François Tetreault
2026TDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement.
Jiarui Wang, Runzhe Tao, Jing Mai, Xun Jiang, Shenghua Wang, Cuiliu Yang, Haoyu Jie, Kan Huang, Richard Y. Sun, Yibo Lin
2026TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs.
Ye Qiao, Zhiheng Chen, Yifan Zhang, Yian Wang, Sitao Huang
2026Towards Scheduling of Pipelined Dataflow Graphs in MLIR.
Gabriel Rodriguez-Canal, Nicolas Bohm Agostini, Ankur Limaye, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo, Maurice Jamieson, Nick Brown
2026UDP: A Universal DSP Packing Framework for Low-bitwidth MAC Acceleration on FPGAs.
Jundong Wu, Zhendong Zheng, Lei Gong, Chao Wang, Xuehai Zhou
2026ViM-Q: Energy Efficient Algorithm-Hardware Co-Design for Dynamically Quantized Vision Mamba Models.
Shengzhe Lyu, Yuhan She, Patrick S. Y. Hung, Ray C. C. Cheung, Weitao Xu
2026vFPGA: Towards Sub-µs Reconfiguration via 3D FPGA and Packaging Co-Design.
Nikhil K. Cherukuri, Sharad Nag, Pragnya Sudershan Nalla, Ashish K. Kola, Chetan S. Gadireddi, Kevin Dai, Jae-sun Seo, Zhenman Fang, Jeff Zhang, Yu Cao