| 2025 | A Unified Framework for Automated Code Transformation and Pragma Insertion. Stéphane Pouget, Louis-Noël Pouchet, Jason Cong |
| 2025 | ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines. Jinming Zhuang, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou |
| 2025 | An Efficient Traversal Method for FPGA Interconnect Testing Based on Regular Routing. Wenwei Chen, Lin Ye, Xiaotong Zhao, Tongshu Ding, Jian Wang, Jinmei Lai |
| 2025 | An Empirical Comparision of LLM-based Hardware Design and High-level Synthesis. Fan Cui, Youwei Xiao, Kexing Zhou, Yun Liang |
| 2025 | Architectures for AI. Steven K. Reinhardt |
| 2025 | BAQET: BRAM-aware Quantization for Efficient Transformer Inference via Stream-based Architecture on an FPGA. LingChi Yang, Chi-Jui Chen, Trung Le, Bo-Cheng Lai, Scott Hauck, Shih-Chieh Hsu |
| 2025 | CIVIC-FPGA: A Trusted FPGA Design Validation by Multi-Tenant Cloud Providers. Yu Feng, Zhaoqi Wang, Christophe Bobda |
| 2025 | DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP. Guoyu Li, Pengbo Zheng, Jian Weng, Enshan Yang |
| 2025 | Dynamic Loop Fusion in High-Level Synthesis. Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede |
| 2025 | Enhancing FPGAs with Analog In-Memory Computing Macros. Archit Gajjar, Lei Zhao, Omar Eldash, Aishwarya Natarajan, Rand Jean, Xia Sheng, Giacomo Pedretti, Paolo Faraboschi, Jim Ignowski, Luca Buonanno |
| 2025 | FAST: FPGA Acceleration of Fully Homomorphic Encryption with Efficient Bootstrapping. Zhihan Xu, Tian Ye, Rajgopal Kannan, Viktor K. Prasanna |
| 2025 | FMC-LLM: Enabling FPGAs for Efficient Batched Decoding of 70B+ LLMs with a Memory-Centric Streaming Architecture. Wenheng Ma, Xinhao Yang, Shulin Zeng, Tengxuan Liu, Libo Shen, Hongyi Wang, Shiyao Li, Jiewen Wang, Yuhan Zhang, Hao Guo, Jintao Li, Ziming Zhang, Zhenhua Zhu, Xuefei Ning, Tsung-Yi Ho, Guohao Dai, Yu Wang |
| 2025 | FPGA Implementation of a 1D-CNN Modulation Classifier for Radar Signals. Edgard Cansio |
| 2025 | FPGA-Only Implementation of MIPI C-PHY Receiver Using Blind Oversampling CDR for CMOS Image Sensors. Jun Yeon Won, Shinki Jeong, Seongkwan Lee, Minho Kang, Insu Yang, Jaemoo Choi |
| 2025 | FPGA-Oriented Design Space Exploration of a Real-Time Road Scene Semantic Segmentation Deep Neural Network. Hugo Le Blevec, Mathieu Léonardon, Stefan Weithoffer, Matthieu Arzel |
| 2025 | FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. Louis Coulon, Lucas Ramirez, Jason Helge Anderson, Mirjana Stojilovic, Paolo Ienne |
| 2025 | FlightVGM: Efficient Video Generation Model Inference with Online Sparsification and Hybrid Precision on FPGAs. Jun Liu, Shulin Zeng, Li Ding, Widyadewi Soedarmadji, Hao Zhou, Zehao Wang, Jinhao Li, Jintao Li, Yadong Dai, Kairui Wen, Shan He, Yaqi Sun, Yu Wang, Guohao Dai |
| 2025 | Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT. Olivia Weng, Marta Andronic, Danial Zuberi, Jiaqing Chen, Caleb Geniesse, George A. Constantinides, Nhan Tran, Nicholas J. Fraser, Javier Mauricio Duarte, Ryan Kastner |
| 2025 | HEDWIG: Homomorphic Encryption Accelerator Design Using BFV-HPS With HiGh-Speed Fixed-Point Approximation. Antian Wang, Weihang Tan, Zhenyu Xu, Tao Wei, Caiwen Ding, Keshab K. Parhi, Yingjie Lao |
| 2025 | HUMA: Heterogeneous, Ultra Low-Latency Model Accelerator for The Virtual Brain on a Versal Adaptive SoC. Amirreza Movahedin, Lennart P. L. Landsmeer, Christos Strydis |
| 2025 | Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration. Shuoxiang Xu, Zijian Jiang, Yuxin Zhang, David Boland, Yungang Bao, Kan Shi |
| 2025 | HiGTR: High-Performance FPGA Implementation of Complete GNN-based Trajectory Reconstruction for HEP. Yun-Chen Yang, Hsuan-Wei Yu, Bo-Cheng Lai, Shih-Chieh Hsu, Mark S. Neubauer, Santosh Parajuli |
| 2025 | High Throughput Low Latency Network Intrusion Detection on FPGAs: A Raw Packet Approach. Muhammad Ali Farooq, Abid Rafique, Suhaib A. Fahmy, Aman Arora |
| 2025 | InTRRA: Inter-Task Resource-Repurposing Accelerator for Efficient Transformer Inference on FPGAs. Zifan He, Hersh Gupta, Huifeng Ke, Jason Cong |
| 2025 | Latency Insensitivity Testing for Dataflow HLS Designs. Jianyi Cheng, Lianghui Wang, Zijian Jiang, Yungang Bao, Kan Shi |
| 2025 | Lessons from 40 Years of Reconfigurable Computing. John Wawrzynek |
| 2025 | Measuring the Minimum Power Requirement of FPGA Architectural Specifications. Andy Gean Ye, Anas Razzaq |
| 2025 | Neural Network Inference in High-Performance Computing: Closing the Gap for FINN based Reconfigurable Accelerators. Linus Jungemann, Bjarne Wintermann, Heinrich Riebler, Christian Plessl |
| 2025 | No Time to Lose: Enabling Real-Time Fluorescence Lifetime Imaging on Resource-constrained FPGAs Through Efficient Scheduling. Ismail Erbas, Aporva Amarnath, Vikas Pandey, Karthik Swaminathan, Naigang Wang, Xavier Intes |
| 2025 | OLA: An FPGA-based Overlay Accelerator for Privacy Preserving Machine Learning with Homomorphic Encryption. Yang Yang, Rajgopal Kannan, Viktor K. Prasanna |
| 2025 | Performance Analysis of GEMM Workloads on the AMD Versal Platform. Kaustubh Manohar Mhatre, Venkata Guru Prasanth Mulleti, Curt John Bansil, Endri Taka, Aman Arora |
| 2025 | PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis. Rui Li, Rajit Manohar |
| 2025 | Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2025, Monterey, CA, USA, 27 February 2025 - 1 March 2025 Andrew Putnam, Jing Li |
| 2025 | RRNS Arith Lib - An Open-Source Redundant Residue Number System Arithmetic VHDL Library. Tim Oberschulte, Enno Sievers, Holger Blume |
| 2025 | ReducedLUT: Table Decomposition with "Don't Care" Conditions. Oliver Cassidy, Marta Andronic, Samuel Coward, George A. Constantinides |
| 2025 | Resource Scheduling for Real-Time Machine Learning. Suyash Vardhan Singh, Iftakhar Ahmad, David Andrews, Miaoqing Huang, Austin R. J. Downey, Jason D. Bakos |
| 2025 | SAT-Accel: A Modern SAT Solver on a FPGA. Michael Lo, Mau-Chung Frank Chang, Jason Cong |
| 2025 | Seamless Acceleration of Fortran Intrinsics via AMD AI Engines. Nick Brown, Gabriel Rodriguez-Canal |
| 2025 | Stream-HLS: Towards Automatic Dataflow Acceleration. Suhail Basalama, Jason Cong |
| 2025 | Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration. Endri Taka, Ning-Chi Huang, Chi-Chih Chang, Kai-Chiang Wu, Aman Arora, Diana Marculescu |
| 2025 | TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms. Enlai Li, Zhe Lin, Sharad Sinha, Wei Zhang |
| 2025 | Tile-Level Pipeline for Linear Scalable Stencil Computation on AMD AI Engines. Zhenyu Xu, Miaoxiang Yu, Yazhe Zhang, Jillian Cai, Qing Yang, Tao Wei |
| 2025 | Towards Accelerator Customization in Real-time Safety-critical Systems. Shixin Ji, Xingzhen Chen, Wei Zhang, Zhuoping Yang, Jinming Zhuang, Sarah Schultz, Yukai Song, Jingtong Hu, Alex K. Jones, Zheng Dong, Peipei Zhou |
| 2025 | TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees. Alireza Khataei, Kia Bazargan |
| 2025 | Two-Phase Transistor Sizing for FPGAs via Bayesian Optimization. Xianfeng Cao, Huizhen Kuang, Yuanqi Wang, Lingli Wang |
| 2025 | wa-hls4ml and lui-gnn: A Benchmark and GNN based Surrogate Model for hls4ml Resource and Latency Estimation. Benjamin Hawks, Dennis Plotnikov, Nhan Tran, Karla Tame-Narvaez, Mohammad Mehdi Rahimifar, Hamza Ezzaoui Rahali, Audrey C. Therrien, Giuseppe Di Guglielmo, Javier Duarte, Vladimir Loncar |