FPGA A

65 papers

YearTitle / Authors
200932-bit floating-point FPGA gaussian elimination.
Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu
20093D configuration caching for 2D FPGAs.
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj
2009A 17ps time-to-digital converter implemented in 65nm FPGA technology.
Claudio Favi, Edoardo Charbon
2009A clustering framework for task partitioning based on function-level data usage analysis.
Sayyed Arash Ostadzadeh, Roel Meeuws, Kamana Sigdel, Koen Bertels
2009A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs.
Dirk Koch, Christian Beckhoff, Jürgen Teich
2009A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation.
David B. Thomas, Lee W. Howes, Wayne Luk
2009A comparison of via-programmable gate array logic cell circuits.
Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang
2009A high performance fpga-based implementation of position specific iterated blast.
Server Kasap, Khaled Benkrid, Ying Liu
2009A high-performance FPGA architecture for restricted boltzmann machines.
Daniel Le Ly, Paul Chow
2009A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer.
Edward C. Lin, Rob A. Rutenbar
2009A novel BIST approach for testing input/output buffers in FPGAs.
Lei Chen, Zhiquan Zhang, Zhiping Wen
2009A novel minloop SB design to improve FPGA routability.
JIanDe Yu, Jinmei Lai
2009A parallel/vectorized double-precision exponential core to accelerate computational science applications.
Robin Pottathuparambil, Ron Sass
2009An intermediate hardware model with load/store unit for C to FPGA.
Akira Yamawaki, Masahiko Iwane
2009Architectural enhancements in Stratix-III
David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan
2009Automatic bus macro placement for partially reconfigurable FPGA designs.
Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin
2009Bus mastering PCI express in an FPGA.
Ray Bittner
2009CMOS vs Nano: comrades or rivals?
Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger
2009Cholesky decomposition using fused datapath synthesis.
Süleyman Sirri Demirsoy, Martin Langhammer
2009Choose-your-own-adventure routing: lightweight load-time defect avoidance.
Raphael Rubin, André DeHon
2009Clock power reduction for virtex-5 FPGAs.
Qiang Wang, Subodh Gupta, Jason Helge Anderson
2009Closed-loop modeling of power and temperature profiles of FPGAs.
Kanupriya Gulati, Sunil P. Khatri, Peng Li
2009Computation reuse in domain-specific optimization of signal recognition.
Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang
2009Customizable bit-width in an OpenMP-based circuit design tool.
Timothy F. Beatty, Eric E. Aubanel, Kenneth B. Kent
2009Data streaming and simd support for the microblaze architecture.
Paul E. Marks, Cameron D. Patterson
2009Diagonal tracks in FPGAs: a performance evaluation.
Sumanta Chaudhuri
2009Emerging application domains: research challenges and opportunities for FPGAs.
Jason Helge Anderson
2009FPCNA: a field programmable carbon nanotube array.
Chen Dong, Scott Chilstedt, Deming Chen
2009FPGA implementation of real-time skin color detection with mean-based surface flattening.
Seunghun Jin, Dongkyun Kim, Thien Cong Pham, Jae Wook Jeon
2009FPGA technology mapping with encoded libraries andstaged priority cuts.
Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox
2009FPGA-based front-end electronics for positron emission tomography.
Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt
2009FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis.
Rosemary M. Francis, Simon W. Moore
2009Fast and scalable packet classification using perfect hash functions.
Viktor Pus, Jan Korenek
2009Flexible multi-mode embedded floating-point unit for field programmable gate arrays.
Yee Jern Chong, Sri Parameswaran
2009Fpga-based face detection system using Haar classifiers.
Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner
2009HMMer acceleration using systolic array based reconfigurable architecture.
Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu
2009HW/SW methodologies for synchronization in FPGA multiprocessors.
Antonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
2009High-performance, cost-effective heterogeneous 3D FPGA architectures.
Roto Le, Sherief Reda, R. Iris Bahar
2009High-performance, energy-efficient platforms using in-socket FPGA accelerators.
Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta
2009Impact and compensation of correlated process variation on ring oscillator based puf.
Abhranil Maiti, Patrick Schaumont
2009Implementation of a genetic algorithm on a virtex-ii pro FPGA.
Michalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou
2009Implementation of the reconfiguration port scheduling on the erlangen slot machine.
Florian Dittmann, Elmar Weber, Norma Montealegre
2009Intel® atom
Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang
2009Large-scale wire-speed packet classification on FPGAs.
Weirong Jiang, Viktor K. Prasanna
2009Making good points: application-specific pareto-point generation for design space exploration using statistical methods.
David Sheldon, Frank Vahid
2009Measuring and modeling variabilityusing low-cost FPGAs.
Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau
2009N-port memory mapping for LUT-based FPGAs.
Zuo Wang, Feng Shi, Qi Zuo, Weixing Ji, Mengxiao Liu
2009PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions.
Johnny Tsung Lin Ho, Guy G. Lemieux
2009Parallel placement for FPGAs revisited.
Cristinel Ababei
2009Performance and power of cache-based reconfigurable computing.
Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig
2009Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009
Paul Chow, Peter Y. K. Cheung
2009Revisiting bitwidth optimizations.
Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou
2009SPR: an architecture-adaptive CGRA mapping tool.
Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck
2009Scalable don't-care-based logic optimization and resynthesis.
Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang
2009Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller.
Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani
2009Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation.
Xinyu Li, Omar Hammami
2009SmartOpt: an industrial strength framework for logic synthesis.
Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton
2009Soft vector processors vs FPGA custom hardware: measuring and reducing the gap.
Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2009Streaming implementation of a sequential decompression algorithm on an FPGA.
Gaurav Mittal, David Zaretsky, Prithviraj Banerjee
2009Synthesis of reconfigurable high-performance multicore systems.
Jason Cong, Karthik Gururaj, Guoling Han
2009The input-aware dynamic adaptation of area and performance for reconfigurable accelerator.
Like Yan, Gang Wang, Tianzhou Chen
2009Towards automated ECOs in FPGAs.
Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour
2009Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.
Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet
2009VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.
Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose
2009Wirelength modeling for homogeneous and heterogeneous FPGA architectural development.
Alastair M. Smith, Steven J. E. Wilton, Joydip Das