FPGA A

47 papers

YearTitle / Authors
2008A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
2008A hardware framework for the fast generation of multiple long-period random number streams.
Ishaan L. Dalal, Deian Stefan
2008A novel FPGA logic block for improved arithmetic performance.
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2008A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design.
David Sheldon, Frank Vahid
2008A type system for static typing of a domain-specific language.
Paul Edward McKechnie, Nathan A. Lindop, Wim Vanderbauwhede
2008A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs.
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2008An integrated debugging environment for FPGA computing platforms.
Kevin Camera, Robert W. Brodersen
2008Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008Architecture-specific packing for virtex-5 FPGAs.
Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal
2008Area and delay trade-offs in the circuit and architecture design of FPGAs.
Ian Kuon, Jonathan Rose
2008Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs.
Michael T. Frederick, Arun K. Somani
2008C is for circuits: capturing FPGA circuits as sequential code for portability.
Scott Sirowy, Greg Stitt, Frank Vahid
2008CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures.
Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan
2008Communication bottleneck in hardware-software partitioning.
Maryam Moazeni, Alireza Vahdatpour, Karthik Gururaj, Majid Sarrafzadeh
2008Configurable decoders with application in fast partial reconfiguration of FPGAs.
Matthew Collin Jordan, Ramachandran Vaidyanathan
2008Designing with extreme parallelism.
Guy G. Lemieux, Tarek A. El-Ghazawi
2008Efficient ASIP design for configurable processors with fine-grained resource sharing.
Quang Dinh, Deming Chen, Martin D. F. Wong
2008Efficient FPGA implementation of qr decomposition using a systolic array architecture.
Xiaojun Wang, Miriam Leeser
2008Efficient tiling patterns for reconfigurable gate arrays.
Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley
2008Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spirals.
Keith So
2008Extreme parallel architectures for the masses.
Tarek A. El-Ghazawi, Guy G. Lemieux
2008FPGA based multiple-channel vibration analyzer for industrial applications with reconfigurable post-processing capabilities for automatic failure detection on machinery.
Luis Miguel Contreras-Medina, René de Jesús Romero-Troncoso, Jose de Jesus Rangel-Magdaleno, Jesus Roberto Millan-Almaraz
2008FPGA implementation of a novel algorithm for on-line bar breakage detection on induction motors.
Jose de Jesus Rangel-Magdaleno, René de Jesús Romero-Troncoso, Luis Miguel Contreras-Medina, Arturo Garcia-Perez
2008FPGA interconnect design using logical effort.
Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong
2008FPGA-optimised high-quality uniform random number generators.
David B. Thomas, Wayne Luk
2008Flexible FPGA-based parallel architecture for identification of repetitive sequences in interleaved pulse trains.
Amin Ansari, Keyvan Amiri
2008Fpga-based data acquisition system for a positron emission tomography (PET) scanner.
Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck
2008From the bitstream to the netlist.
Jean-Baptiste Note, Éric Rannaud
2008High-quality, deterministic parallel placement for FPGAs on commodity hardware.
Adrian Ludwin, Vaughn Betz, Ketan Padalia
2008High-throughput interconnect wave-pipelining for global communication in FPGAs.
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008HybridOS: runtime support for reconfigurable accelerators.
John H. Kelm, Steven S. Lumetta
2008Implementing high-speed string matching hardware for network intrusion detection systems.
Atul Mahajan, Benfano Soewito, Sai K. Parsi, Ning Weng, Haibo Wang
2008Lithographic aerial image simulation with FPGA-based hardwareacceleration.
Jason Cong, Yi Zou
2008Mapping for better than worst-case delays in LUT-based FPGA designs.
Kirill Minkovich, Jason Cong
2008Measuring and modeling FPGA clock variability.
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008Modeling routing demand for early-stage FPGA architecture development.
Wei Mark Fang, Jonathan Rose
2008Pattern-based behavior synthesis for FPGA resource reduction.
Jason Cong, Wei Jiang
2008Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008
Mike Hutton, Paul Chow
2008Reconfigurable computing for learning Bayesian networks.
Narges Bani Asadi, Teresa H. Meng, Wing Hung Wong
2008Retrieving 3-d information with FPGA-based stream processing.
Hidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata, Kiyoshi Oguri
2008Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.
Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
2008TORCH: a design tool for routing channel segmentation in FPGAs.
Mingjie Lin, Abbas El Gamal
2008The amorphous FPGA architecture.
Mingjie Lin
2008Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.
Lerong Cheng, Yan Lin, Lei He
2008Vector processing as a soft-core CPU accelerator.
Jason Yu, Guy G. Lemieux, Christopher Eagleston
2008When FPGAs are better at floating-point than microprocessors.
Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran
2008WireMap: FPGA technology mapping for improved routability.
Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko