FPGA A

53 papers

YearTitle / Authors
2006A 90nm low-power FPGA for battery-powered applications.
Tim Tuan, Sean Kao, Arifur Rahman, Satyaki Das, Steven Trimberger
2006A Performance model for accelerating scientific applications on reconfigurable computers.
Ronald Scrofano, Viktor K. Prasanna
2006A compact FPGA implementation of the hash function whirlpool.
Norbert Pramstaller, Christian Rechberger, Vincent Rijmen
2006A generic lookup cache architecture for network processing applications.
Janardhan Singaraju, John A. Chandy
2006A multilevel hierarchical interconnection structure for FPGA.
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
2006A novel methodology for designing high-performance and low-energy FPGA routing architecture.
Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis
2006A programmable majority logic array using molecular scale electronics.
Garrett S. Rose, Mircea R. Stan
2006A real-time implementation of Richardson-Lucy deconvolution.
Oliver Sims, James Irvine
2006A reconfigurable architecture for hybrid CMOS/Nanodevice circuits.
Dmitri B. Strukov, Konstantin K. Likharev
2006A reconfigurable architecture for network intrusion detection using principal component analysis.
David T. Nguyen, Gokhan Memik, Alok N. Choudhary
2006A reconfigurable hardware based embedded scheduler for buffered crossbar switches.
Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis
2006A type architecture for hybrid micro-parallel computers.
Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling
2006An adaptive Reed-Solomon errors-and-erasures decoder.
Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier
2006An iterative division algorithm for FPGAs.
Jianhua Liu, Michael Chang, Chung-Kuan Cheng
2006Application-specific customization of soft processor microarchitecture.
Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
2006Armada: timing-driven pipeline-aware routing for FPGAs.
Kenneth Eguro, Scott Hauck
2006Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices.
Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura
2006Building a flexible and scalable DRAM interface for networking applications on FPGAs.
Jike Chong, Chidamber Kulkarni, Gordon J. Brebner
2006Combining module selection and resource sharing for efficient FPGA pipeline synthesis.
Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer
2006Configuration tools for a new multilevel hierarchical FPGA.
Zied Marrakchi, Hayder Mrabet, Habib Mehrez
2006Context-free-grammar based token tagger in reconfigurable devices.
Young H. Cho, James Moscola, John W. Lockwood
2006Design, implementation, and verification of active cache emulator (ACE).
Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu
2006Effective clustering technique to optimize routability of outer cluster nets.
Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi
2006Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic.
Joshua Noseworthy, Miriam Leeser
2006Embedded floating-point units in FPGAs.
Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert
2006Evaluation of granularity on threshold voltage control in flex power FPGA.
Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
2006FPGA based RAID 6 hardware accelerator.
Michael P. Gilroy, James Irvine, William Berrie
2006FPGA clock network architecture: flexibility vs. area and power.
Julien Lamoureux, Steven J. E. Wilton
2006FPGAs with multidimensional mesh topology.
Yohei Matsumoto, Hanpei Koike, Akira Masaki
2006Fast and accurate resource estimation of automatically generated custom DFT IP cores.
Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel
2006Fine-grained island style architecture for molecular electronic devices.
Mohammad Tehranipoor, Reza M. Rad
2006Flexible implementation of genetic algorithms on FPGAs.
Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata, Keiichi Yasumoto, Minoru Ito
2006GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systems.
Milan Tichý, Andy Nisbet, David Gregg
2006High speed FIR filter implementation using add and shift method.
Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner
2006Improvements to technology mapping for LUT-based FPGAs.
Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
2006Improving performance and robustness of domain-specific CPLDs.
Mark Holland, Scott Hauck
2006Jaguar: a compiler infrastructure for Java reconfigurable computing.
Youngsun Han, Seokjoong Hwang, Seon Wook Kim
2006Magnetic tunnelling junction based FPGA.
Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon
2006Manifold similarity search of DNA sequences with reconfigurable hardware.
Thinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama
2006Measuring the gap between FPGAs and ASICs.
Ian Kuon, Jonathan Rose
2006Modeling the data-dependent performance of pattern-matching architectures.
Christopher R. Clark, David E. Schimmel
2006Optimality study of logic synthesis for LUT-based FPGAs.
Jason Cong, Kirill Minkovich
2006Performance benefits of monolithically stacked 3D-FPGA.
Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong
2006Periodic licensing of FPGA based intellectual property.
Nathaniel Couture, Kenneth B. Kent
2006Post-placement interconnect entropy.
Wenyi Feng, Jonathan W. Greene
2006Power-aware RAM mapping for FPGA embedded memory blocks.
Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy
2006Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006
Steven J. E. Wilton, André DeHon
2006Reconfigurable computing with multiscale data fusion for remote sensing.
Vikas Aggarwal, Alan D. George, K. Clint Slatton
2006Simulative analysis of dynamic scheduling heuristics for reconfigurable computing of parallel applications.
Rajagopal Subramaniyan, Ian A. Troxel, Alan D. George, Melissa C. Smith
2006Test and recovery for fine-grained nanoscale architectures.
Mohammad Tehranipoor, Reza M. Rad
2006Testing embedded RAM modules in SRAM-based FPGAs.
Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali
2006The routability of multiprocessor network topologies in FPGAs.
Manuel Saldaña, Lesley Shannon, Paul Chow
2006Yield enhancements of design-specific FPGAs.
Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko