FPGA A

65 papers

YearTitle / Authors
20053D FPGAs: placement, routing, and architecture evaluation (abstract only).
Cristinel Ababei, Hushrav Mogal, Kia Bazargan
20053D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only).
Chul Kim, A. M. Rassau, Mike Myung-Ok Lee
200564-bit floating-point FPGA matrix multiplication.
Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev
2005A 2005 review of FPGA arithmetic (abstract only).
Stéphane Simard, Rachid Beguenane, Éric Larouche, Luc Morin
2005A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only).
Yirong OuYang, Jiarong Tong
2005A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only).
Edward D. Moreno, Fábio Dacêncio Pereira, Rodolfo B. Chiaramonte
2005A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only).
Bo Yang, Nikhil Joshi, Ramesh Karri
2005A framework for rule processing in reconfigurable network systems (abstract only).
Michael Attig, John W. Lockwood
2005A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only).
Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
2005A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only).
Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusébio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino Silva-Filho
2005A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only).
Remy Eskinazi Sant'Anna, Manoel Eusébio de Lima, Paulo Romero Martins Maciel, Carlos A. Valderrama, Abel Guilhermino Silva-Filho, Paulo Sérgio B. do Nascimento
2005Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only).
Jianchun Li, Christos A. Papachristou, Raj Shekhar
2005An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only).
Sven Heithecker, Rolf Ernst
2005An FPGA generator for multipoint distributed random variables (abstract only).
Nicola Bruti Liberati, Eckhard Platen, Filippo Martini, Massimo Piccardi
2005An FPGA-based VLIW processor with custom hardware execution.
Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster
2005An execution environment for reconfigurable computing (abstract only).
Wenyin Fu, Katherine Compton
2005An integrated framework for the high level design of high performance signal processing circuits on FPGAs (abstract only).
Khaled Benkrid, Samir Belkacemi
2005Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.
Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2005Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only).
Akshay Sharma, Carl Ebeling, Scott Hauck
2005Automated synthesis for asynchronous FPGAs.
Song Peng, David Fang, John Teifel, Rajit Manohar
2005CUSP: a modular framework for high speed network applications on FPGAs.
Graham Schelle, Dirk Grunwald
2005Choice of base revisited: higher radices for FPGA-based floating-point computation (abstract only).
Bryan Catanzaro, Brent E. Nelson
2005Combining low-leakage techniques for FPGA routing design.
Andrea Lodi, Luca Ciccarelli, Roberto Giansante
2005Configurable hardware solutions for computing autocorrelation coefficients: a case study (abstract only).
Jacqueline E. Rice, Kenneth B. Kent, Troy Ronda, Zhao Yong
2005Design and implementation of packet classification with FPGA (abstract only).
Yong-Gang Wang, Tian-Xin Yan
2005Design of programmable interconnect for sublithographic programmable logic arrays.
André DeHon
2005Design, layout and verification of an FPGA using automated tools.
Ian Kuon, Aaron Egier, Jonathan Rose
2005Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only).
Wen Yujie, Jiarong Tong, Charles C. Chiang
2005Dual-Vt FPGA design for leakage power reduction (abstract only).
Akhilesh Kumar, Mohab Anis
2005Dynamic hardware multiplexing for coarse grain reconfigurable architectures.
Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon
2005Dynamic reconfiguration in FPGA-based SoC designs (abstract only).
Roman Bartosinski, Martin Danek, Petr Honzík, Rudolf Matousek
2005Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only).
E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan
2005Efficient packet classification for network intrusion detection using FPGA.
Haoyu Song, John W. Lockwood
2005Efficient static timing analysis and applications using edge masks.
Mike Hutton, David Karchmer, Bryan Archell, Jason Govig
2005Efficient utilization of heterogeneous routing resources for FPGAs (abstract only).
Deepak Rautela, Rajendra S. Katti
2005Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only).
Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel
2005Energy-efficient FPGA interconnect architecture design (abstract only).
Rohini Krishnan, R. I. M. P. Meijer, Durand Guillaume
2005Evaluating heuristics in automatically mapping multi-loop applications to FPGAs.
Heidi E. Ziegler, Mary W. Hall
2005Exploration of heterogeneous reconfigurable architectures (abstract only).
Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung
2005Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only).
Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl
2005Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only).
Roman L. Lysecky, Kris Miller, Frank Vahid, Kees A. Vissers
2005Floating-point sparse matrix-vector multiply for FPGAs.
Michael DeLorimier, André DeHon
2005HARP: hard-wired routing pattern FPGAs.
Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh
2005Hierarchical LUT structures for leakage power reduction (abstract only).
Somsubhra Mondal, Seda Ogrenci Memik, Debasish Das
2005Hyper customized processors for bio-sequence database scanning on FPGAs.
Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell
2005Image processing library for reconfigurable computers (abstract only).
Mohamed Taher, Esam El-Araby, Tarek A. El-Ghazawi, Kris Gaj
2005Instruction set extension with shadow registers for configurable processors.
Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang
2005Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.
Yan Lin, Fei Li, Lei He
2005Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005
Herman Schmit, Steven J. E. Wilton
2005Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only).
Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
2005Rapid prototyping of a test harness for forward error correcting codes (abstract only).
Edward Brown, James Irvine, Bill Wilkie
2005Reconfigurable computers: an empirical analysis (abstract only).
Tarek A. El-Ghazawi, Kris Gaj, Nikitas A. Alexandridis, Allen Michalski, Osman Devrim Fidanci, Mohamed Taher, Esam El-Araby, Esmail Chitalwala, Proshanta Saha
2005Routing algorithms: enhancing routability & enabling ECO (abstract only).
Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh
2005SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only).
Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee
2005Simultaneous timing-driven placement and duplication.
Gang Chen, Jason Cong
2005Skew-programmable clock design for FPGA and skew-aware placement.
Chao-Yang Yeh, Malgorzata Marek-Sadowska
2005Soft error rate estimation and mitigation for SRAM-based FPGAs.
Ghazanfar Asadi, Mehdi Baradaran Tahoori
2005Soft multiprocessor systems for network applications (abstract only).
Yujia Jin, William Plishker, Kaushik Ravindran, Nadathur Satish, Kurt Keutzer
2005Sparse Matrix-Vector multiplication on FPGAs.
Ling Zhuo, Viktor K. Prasanna
2005Techniques for synthesizing binaries to an advanced register/memory structure.
Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
2005The Stratix II logic and routing architecture.
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose
2005The effect of post-layout pin permutation on timing.
Yuzheng Ding, Peter Suaris, Nan-Chi Chou
2005Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation.
Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano
2005Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits.
Andy Gean Ye, Jonathan Rose
2005VPart: an automatic partitioning tool for dynamic reconfiguration (abstract only).
Leos Kafka, Rafal Kielbik, Rudolf Matousek, Juan Manuel Moreno