FPGA A

68 papers

YearTitle / Authors
2004A VHDL MPEG-7 shape descriptor extractor.
Bret Woz, Andreas E. Savakis
2004A compiled accelerator for biological cell signaling simulations.
John F. Keane, Christopher Bradley, Carl Ebeling
2004A constraints programming approach to communication scheduling on SoPC architectures.
Christophe Wolinski, Krzysztof Kuchcinski, Maya B. Gokhale
2004A flexible hardware architecture for 2-D discrete wavelet transform.
Richard Carbone, Andreas E. Savakis
2004A high performance 32-bit ALU for programmable logic.
Paul Metzgen
2004A left-edge algorithm approach for scheduling and allocation of hardware contexts in dynamically reconfigurable architectures.
Remy Eskinazi Sant'Anna, Manoel Eusébio de Lima, Paulo Romero Martins Maciel
2004A magnetoelectronic macrocell employing reconfigurable threshold logic.
Steve Ferrera, Nicholas P. Carter
2004A novel coarse-grain reconfigurable data-path for accelerating DSP kernels.
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
2004A quantitative analysis of the speedup factors of FPGAs over processors.
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers
2004A reconfigurable unit for a clustered programmable-reconfigurable processor.
Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter
2004A synthesis oriented omniscient manual editor.
Tomasz S. Czajkowski, Jonathan Rose
2004Active leakage power optimization for FPGAs.
Jason Helge Anderson, Farid N. Najm, Tim Tuan
2004Addressing application integrity attacks using a reconfigurable architecture.
Joseph Zambreno, Rahul Simha, Alok N. Choudhary
2004An FPGA implementation of bene permutation networks.
Anatole D. Ruslanov, Jeremy R. Johnson
2004An FPGA implementation of block truncation coding for gray and color images.
Sherif M. Saif, Hazem M. Abbas, Salwa M. Nassar
2004An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm.
Wang Chen, Panos Kosmas, Miriam Leeser, Carey M. Rappaport
2004An FPGA prototype for the experimental evaluation of a multizone network cache.
Paul Berube, José Nelson Amaral, Mike H. MacGregor
2004An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design.
Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee
2004An algorithmic approach by heuristics to dynamical reconfiguration of logic resources on reconfigurable FPGAs.
Phan Cong Vinh, Jonathan P. Bowen
2004An embedded true random number generator for FPGAs.
Paul Kohlbrenner, Kris Gaj
2004Application-specific instruction generation for configurable processor architectures.
Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang
2004Automatic discovery, selection, and specialization of modules in RCADE.
Ranjesh G. Jaganathan, Matthew Simpson, Ron Sass
2004Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier.
Jae-Jin Lee, Gi-Yong Song
2004Buffer schemes for runtime reconfiguration of function variants in communication systems.
Helmut Steckenbiller, Rudi Knorr
2004Divide and concatenate: a scalable hardware architecture for universal MAC.
Bo Yang, Ramesh Karri, David A. McGrew
2004Dynamically reconfigurable architecture for high-throughput processing of data centric applications.
Magesh Sadasivam, Sangjin Hong
2004Evaluation of low-leakage design techniques for field programmable gate arrays.
Arifur Rahman, Vijay Polavarapuv
2004Exploration of pipelined FPGA interconnect structures.
Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck
2004FPGA implementation of a high speed network interface card for optical burst switched networks.
Pronita Mehrotra, Mrugendra Singhai, Mike Pratt, Mark Cassada, Patrick Hamilton
2004FPGA modelling for high-performance algorithms.
Martin Danek, Josef Kolár
2004FPGA-based implementation of single-precision exponential unit.
Christopher C. Doss, Robert L. Riley Jr.
2004FPGA-based supercomputing: an implementation for molecular dynamics.
Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow
2004FPGAs vs. CPUs: trends in peak floating-point performance.
Keith D. Underwood
2004Fast adders in modern FPGAs.
Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris
2004Flexibility measurement of domain-specific reconfigurable hardware.
Katherine Compton, Scott Hauck
2004Hardware co-simulation in system generator of the AES-128 encryption algorithm.
Daniel Denning, Malachy Devlin, James Irvine
2004High level area, delay and power estimation for FPGAs.
Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee
2004High-speed systolic array for gene matching.
Gabriel Caffarena, Slobodan Bojanic, Juan A. López, Carlos E. Pedreira, Octavio Nieto-Taladriz
2004Highly pipelined asynchronous FPGAs.
John Teifel, Rajit Manohar
2004Implementation of elliptic curve cryptosystems over GF(2
Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi
2004Improving the reliability of FPGA circuits using triple-modular redundancy (TMR) & efficient voter placement.
Michael J. Wirthlin
2004In-system FPGA prototyping of an itanium microarchitecture.
Roland E. Wunderlich, James C. Hoe
2004Incremental physical resynthesis for timing optimization.
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou
2004Least-significant bit optimization techniques for FPGAs.
Mark L. Chang, Scott Hauck
2004Low energy FPGA interconnect design.
Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek
2004Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.
Fei Li, Yan Lin, Lei He, Jason Cong
2004Low-power technology mapping for FPGA architectures with dual supply voltages.
Deming Chen, Jason Cong, Fei Li, Lei He
2004Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report.
Sergio López-Buedo, Eduardo I. Boemo
2004Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources.
Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis
2004Nanowire-based sublithographic programmable logic arrays.
André DeHon, Michael J. Wilson
2004On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs.
Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
2004Online placement infrastructure to support run-time reconfiguration.
Brian Leonard, Jeff Young, Ron Sass
2004Power analysis and estimation tool integrated with XPOWER.
Elias Todorovich, Eduardo I. Boemo, Francisco Cardells-Tormo, Javier Valls
2004Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity.
Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike
2004Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004
Russell Tessier, Herman Schmit
2004Reducing leakage energy in FPGAs using region-constrained placement.
Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan
2004Routing architecture for multi-context FPGAs.
Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Mario Toma, Fabio Campi
2004Roving testing using new built-in-self-tester designs for FPGAs.
Vinay Verma, Shantanu Dutt
2004SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis.
A. Manoj Kumar, B. Jayaram, V. Kamakoti
2004SPFD-based one-to-many rewiring.
Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi
2004Subframe multiplexing for FPGA manufacturing test configuration.
Erik Chmelar
2004The SFRA: a corner-turn FPGA architecture.
Nicholas Weaver, John R. Hauser, John Wawrzynek
2004The gigahertz FPGA: design consideration and applications.
Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald
2004Time and area efficient pattern matching on FPGAs.
Zachary K. Baker, Viktor K. Prasanna
2004Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs.
Ian Kuon, Aaron Egier, Jonathan Rose
2004Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger.
Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller
2004Using reconfigurability to achieve real-time profiling for hardware/software codesign.
Lesley Shannon, Paul Chow
2004What is the right model for programming and using modern FPGAs?
André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica