| 2018 | 2018 Formal Methods in Computer Aided Design, FMCAD 2018, Austin, TX, USA, October 30 - November 2, 2018 Nikolaj S. Bjørner, Arie Gurfinkel |
| 2018 | A Verified Certificate Checker for Finite-Precision Error Bounds in Coq and HOL4. Heiko Becker, Nikita Zyuzin, Raphaël Monat, Eva Darulova, Magnus O. Myreen, Anthony C. J. Fox |
| 2018 | Analysis of Relay Interlocking Systems via SMT-based Model Checking of Switched Multi-Domain Kirchhoff Networks. Roberto Cavada, Alessandro Cimatti, Sergio Mover, Mirko Sessa, Giuseppe Cadavero, Giuseppe Scaglione |
| 2018 | Analyzing the Fundamental Liveness Property of the Chord Protocol. Julien Brunel, David Chemouil, Jeanne Tawa |
| 2018 | Automata Learning for Symbolic Execution. Bernhard K. Aichernig, Roderick Bloem, Masoud Ebrahimi, Martin Tappler, Johannes Winter |
| 2018 | Automatic Synchronization for GPU Kernels. Sourav Anand, Nadia Polikarpova |
| 2018 | BMC with Memory Models as Modules. Hernán Ponce de León, Florian Furbach, Keijo Heljanko, Roland Meyer |
| 2018 | Bit-Vector Interpolation and Quantifier Elimination by Lazy Reduction. Peter Backeman, Philipp Rümmer, Aleksandar Zeljic |
| 2018 | Certifying Proofs for LTL Model Checking. Alberto Griggio, Marco Roveri, Stefano Tonetta |
| 2018 | CoSA: Integrated Verification for Agile Hardware Design. Cristian Mattarei, Makai Mann, Clark W. Barrett, Ross G. Daly, Dillon Huff, Pat Hanrahan |
| 2018 | Complete Test Sets And Their Approximations. Eugene Goldberg |
| 2018 | Complete and Efficient DRAT Proof Checking. Adrian Rebola-Pardo, Luís Cruz-Filipe |
| 2018 | Deductive Verification of Distributed Protocols in First-Order Logic. Oded Padon |
| 2018 | Design-Time Railway Capacity Verification using SAT modulo Discrete Event Simulation. Bjørnar Luteberget, Koen Claessen, Christian Johansen |
| 2018 | Expansion-Based QBF Solving Without Recursion. Roderick Bloem, Nicolas Braud-Santoni, Vedad Hadzic, Uwe Egly, Florian Lonsing, Martina Seidl |
| 2018 | Formal Verification of Deep Neural Networks. Nina Narodytska |
| 2018 | Functional Synthesis via Input-Output Separation. Supratik Chakraborty, Dror Fried, Lucas M. Tabajara, Moshe Y. Vardi |
| 2018 | ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification. Hongce Zhang, Caroline Trippel, Yatin A. Manerkar, Aarti Gupta, Margaret Martonosi, Sharad Malik |
| 2018 | Learning Linear Temporal Properties. Daniel Neider, Ivan Gavran |
| 2018 | Post-Verification Debugging and Rectification of Finite Field Arithmetic Circuits using Computer Algebra Techniques. Vikas Rao, Utkarsh Gupta, Irina Ilioaea, Arpitha Srinath, Priyank Kalla, Florian Enescu |
| 2018 | Rely-Guarantee Reasoning for Automated Bound Analysis of Lock-Free Algorithms. Thomas Pani, Georg Weissenbacher, Florian Zuleger |
| 2018 | Semantic-based Automated Reasoning for AWS Access Policies using SMT. John Backes, Pauline Bolignano, Byron Cook, Catherine Dodge, Andrew Gacek, Kasper Søe Luckow, Neha Rungta, Oksana Tkachuk, Carsten Varming |
| 2018 | Solving Constrained Horn Clauses Using Syntax and Data. Grigory Fedyukovich, Sumanth Prabhu, Kumar Madhukar, Aarti Gupta |
| 2018 | Template-Based Verification of Heap-Manipulating Programs. Viktor Malík, Martin Hruska, Peter Schrammel, Tomás Vojnar |
| 2018 | Temporal Prophecy for Proving Temporal Properties of Infinite-State Systems. Oded Padon, Jochen Hoenicke, Kenneth L. McMillan, Andreas Podelski, Mooly Sagiv, Sharon Shoham |
| 2018 | The ELDARICA Horn Solver. Hossein Hojjat, Philipp Rümmer |
| 2018 | The FMCAD 2018 Graduate Student Forum. Dejan Jovanovic, Andrew Reynolds |
| 2018 | Trau: SMT solver for string constraints. Parosh Aziz Abdulla, Mohamed Faouzi Atig, Yu-Fang Chen, Bui Phi Diep, Lukás Holík, Ahmed Rezine, Philipp Rümmer |
| 2018 | Using Loop Bound Analysis For Invariant Generation. Pavel Cadek, Clemens Danninger, Moritz Sinn, Florian Zuleger |
| 2018 | k-FAIR = k-LIVENESS + FAIR Revisiting SAT-based Liveness Algorithms. Alexander Ivrii, Ziv Nevo, Jason Baumgartner |