FMCAD B

27 papers

YearTitle / Authors
2006A Formal Model of Lower System Layers.
Julien Schmaltz
2006A Refinement Method for Validity Checking of Quantified First-Order Formulas in Hardware Verification.
Husam Abu-Haimed, David L. Dill, Sergey Berezin
2006ACL2SIX: A Hint used to Integrate a Theorem Prover and an Automated Verification Tool.
Jun Sawada, Erik Reeber
2006Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling.
Florian Pigorsch, Christoph Scholl, Stefan Disch
2006An Improved Distance Heuristic Function for Directed Software Model Checking.
Neha Rungta, Eric G. Mercer
2006An Integration of HOL and ACL2.
Michael J. C. Gordon, James Reynolds, Warren A. Hunt Jr., Matt Kaufmann
2006Ario: A Linear Integer Arithmetic Logic Solver.
Hossein M. Sheini, Karem A. Sakallah
2006Assume-Guarantee Reasoning for Deadlock.
Sagar Chaki, Nishant Sinha
2006Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip.
Claude Helmstetter, Florence Maraninchi, Laurent Maillet-Contoz, Matthieu Moy
2006Design for Verification of the PCI-X Bus.
Haja Moinudeen, Ali Habibi, Sofiène Tahar
2006Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning.
Tilman Glökler, Jason Baumgartner, Devi Shanmugam, A. E. (Rick) Seigler, Gary A. Van Huben, Barinjato Ramanandray, Hari Mony, Paul Roessler
2006Finite Instantiations for Integer Difference Logic.
Hyondeuk Kim, Fabio Somenzi
2006Formal Analysis and Verification of an OFDM Modem Design using HOL.
Abu Nasser Mohammed Abdullah, Behzad Akbarpour, Sofiène Tahar
2006Formal Methods in Computer-Aided Design, 6th International Conference, FMCAD 2006, San Jose, California, USA, November 12-16, 2006, Proceedings
2006From PSL to NBA: a Modular Symbolic Encoding.
Alessandro Cimatti, Marco Roveri, Simone Semprini, Stefano Tonetta
2006Liveness and Boundedness of Synchronous Data Flow Graphs.
Amir Hossein Ghamarian, Marc Geilen, Twan Basten, Bart D. Theelen, Mohammad Reza Mousavi, Sander Stuijk
2006Model Checking Data-Dependent Real-Time Properties of the European Train Control System.
Johannes Faber, Roland Meyer
2006Optimizations for LTL Synthesis.
Barbara Jobstmann, Roderick Bloem
2006Over-Approximating Boolean Programs with Unbounded Thread Creation.
Byron Cook, Daniel Kroening, Natasha Sharygina
2006Post-reboot Equivalence and Compositional Verification of Hardware.
Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
2006Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee.
Xiaofang Chen, Yu Yang, Ganesh Gopalakrishnan, Ching-Tsun Chou
2006Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands.
Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu
2006Symmetry Reduction for STE Model Checking.
Ashish Darbari
2006Synchronous Elastic Networks.
Sava Krstic, Jordi Cortadella, Michael Kishinevsky, John O'Leary
2006Thorough Checking Revisited.
Shiva Nejati, Mihaela Gheorghiu, Marsha Chechik
2006Tracking MUSes and Strict Inconsistent Covers.
Éric Grégoire, Bertrand Mazure, Cédric Piette
2006Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis.
Cameron Brien, Sharad Malik