| 1998 | A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. Nazanin Mansouri, Ranga Vemuri |
| 1998 | A Performance Study of BDD-Based Model Checking. Bwolen Yang, Randal E. Bryant, David R. O'Hallaron, Armin Biere, Olivier Coudert, Geert Janssen, Rajeev K. Ranjan, Fabio Somenzi |
| 1998 | A Tutorial on Stålmarcks's Proof Procedure for Propositional Logic. Mary Sheeran, Gunnar Stålmarck |
| 1998 | Alexandria: A Tool for Hierarchical Verification. Annette Bunker, Trent N. Larson, Michael D. Jones, Phillip J. Windley |
| 1998 | Almana: A BDD Minimization Tool Integrating Heuristic and Rewriting Methods. Macha Nikolskaïa, Antoine Rauzy, David James Sherman |
| 1998 | An Assume-Guarantee Rule for Checking Simulation. Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran |
| 1998 | An Instruction Set Process Calculus. Shiu-Kai Chin, Jang Dae Kim |
| 1998 | Automatic Verification of Mixed-Level Logic Circuits. F. Keith Hanna |
| 1998 | BDDNOW: A Parallel BDD Package. Kim Milvang-Jensen, Alan J. Hu |
| 1998 | Bisimulation Minimization in an Automata-Theoretic Verification Framework. Kathi Fisler, Moshe Y. Vardi |
| 1998 | Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking. Miroslav N. Velev, Randal E. Bryant |
| 1998 | Combined Formal Post- and Presynthesis Verification in High Level Synthesis. Thomas Lock, Michael Mendler, Matthias Mutz |
| 1998 | Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification. Sergey Berezin, Armin Biere, Edmund M. Clarke, Yunshan Zhu |
| 1998 | Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. Justin E. Harlow III, Franc Brglez |
| 1998 | Formal Methods in CAD from an Industrial Perspective (abstract). Carl-Johan H. Seger |
| 1998 | Formal Methods in Computer-Aided Design, Second International Conference, FMCAD '98, Palo Alto, California, USA, November 4-6, 1998, Proceedings Ganesh Gopalakrishnan, Phillip J. Windley |
| 1998 | Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem. Abdelillah Mokkedem, Ravi Hosabettu, Ganesh Gopalakrishnan |
| 1998 | Formally Verifying Data and Control with Weak Reachability Invariants. Jeffrey X. Su, David L. Dill, Jens U. Skakkebæk |
| 1998 | Generalized Reversible Rules. C. Norris Ip |
| 1998 | Input Elimination and Abstraction in Model Checking. Sela Mador-Haim, Limor Fix |
| 1998 | Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints. Fen Jin, Henrik Hulgaard, Eduard Cerny |
| 1998 | Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification (abstract). Kenneth L. McMillan |
| 1998 | Model Checking VHDL with CV. David Déharbe, Subash Shankar, Edmund M. Clarke |
| 1998 | Model Checking on Product Structures. Klaus Schneider |
| 1998 | PV: An Explicit Enumeration Model-Checker. Ratan Nalumasu, Ganesh Gopalakrishnan |
| 1998 | Reducing Manual Abstraction in Formal Verification of Out-of-Order Execution. Robert B. Jones, Jens U. Skakkebæk, David L. Dill |
| 1998 | Solving Bit-Vector Equations. M. Oliver Möller, Harald Rueß |
| 1998 | Symbolic Model Checking Visualization. Gila Kamhi, Limor Fix, Ziv Binyamini |
| 1998 | Symbolic Simulation of the JEM1 Microprocessor. David A. Greve |
| 1998 | Symbolic Simulation: An ACL2 Approach. J Strother Moore |
| 1998 | Techniques for Implicit State Enumeration of EFSMs. James H. Kukula, Thomas R. Shiple, Adnan Aziz |
| 1998 | The Formal Design of 1M-gate ASICs. Ásgeir Th. Eiríksson |
| 1998 | Three Approaches to Hardware Verification: HOL, MDG and VIS Compared. Sofiène Tahar, Paul Curzon, Jianping Lu |
| 1998 | Using MTBDDs for Compostion and Model Checking of Real-Time Systems. Jürgen Ruf, Thomas Kropf |
| 1998 | Verification of Data-Insensitive CIrcuits: An In-Order-Retirement Case Study. Amir Pnueli, Tamarah Arons |