ETS B

55 papers

YearTitle / Authors
201621th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016
2016A 40Gbps economic extension board and FPGA-based testing platform.
Te-Hui Chen, David C. Keezer
2016A built-in method for measuring the delay of TSVs in 3D ICs.
Han-Yu Wu, Yong-Xiao Chen, Jin-Fu Li
2016A design-for-test solution for monolithic 3D integrated circuits.
Ran Wang, Krishnendu Chakrabarty
2016A fast sweep-line-based failure pattern extractor for memory diagnosis.
Sin-Yu Wei, Bing-Yang Lin, Cheng-Wen Wu
2016A hybrid algorithm to conservatively check the robustness of circuits.
Niels Thole, Lorena Anghel, Görschwin Fey
2016A low-cost susceptibility analysis methodology to selectively harden logic circuits.
Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2016A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs.
Boyang Du, Luca Sterpone, David Merodio Codinachs
2016A novel test generation and application flow for functional access to IEEE 1687 instruments.
Michele Portolan
2016A novel threshold voltage defined switch for circuit camouflaging.
Ithihasa Reddy Nirmala, Deepak Vontela, Swaroop Ghosh, Anirudh Iyengar
2016A scheduling method for hierarchical testability based on test environment generation results.
Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara
2016A self-reconfiguring IEEE 1687 network for fault monitoring.
Farrokh Ghani Zadegan, Dimitar Nikolov, Erik Larsson
2016Addressing transient routing errors in fault-tolerant Networks-on-Chips.
Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis
2016An optical/electrical test system for 100Gb/s optical interconnection devices with high volume testing capability.
Tasuku Fujibe, Kazuki Shirahata, Takeshi Mizushima, Hidenobu Matsumura, Daisuke Watanabe, Hiroyuki Mineo, Shin Masuda
2016Analysis and design of an on-chip retargeting engine for IEEE 1687 networks.
Ahmed Ibrahim, Hans G. Kerkhoff
2016Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing.
Abhishek Koneru, Krishnendu Chakrabarty
2016Automotive embedded software architecture in the multi-core age.
Paolo Gai, Massimo Violante
2016Behavior and test of open-gate defects in FinFET based cells.
Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac
2016Bit-flip detection-driven selection of trace signals.
Amin Vali, Nicola Nicolici
2016CPE: Codeword Prediction Encoder.
Satish Grandhi, Elsa Dupraz, Christian Spagnol, Valentin Savin, Emanuel M. Popovici
2016Cell Aware and stuck-open tests.
Adit D. Singh
2016Cell-aware diagnosis: Defective inmates exposed in their cells.
Peter C. Maxwell, Friedrich Hapke, Huaxing Tang
2016Combining the histogram method and the ultrafast segmented model identification of linearity errors algorithm for ADC linearity testing.
Weida Chen, Yongxin Zhu, Xinyi Liu, Xinyang Li, Dongyu Ou
2016Component fault localization using switching current measurements.
Seetal Potluri, Satya Trinadh, Siddhant Saraf, Kamakoti Veezhinathan
2016Compressor design for silicon debug.
Jing Zhang, Lars-Johan Fritz, Liang Liu, Erik Larsson
2016Cross-layer resilience.
Subhasish Mitra
2016ETS 2015 best paper.
Hans-Joachim Wunderlich, Peter C. Maxwell
2016ETS 2016 foreword.
Said Hamdioui, Giorgio Di Natale, Bram Kruseman, Maria K. Michael, Haralampos-G. D. Stratigopoulos
2016Failure mechanisms and test methods for the SRAM TVC write-assist technique.
Josef Kinseher, Moritz Völker, Leonardo Bonet Zordan, Ilia Polian
2016Formal verification of secure reconfigurable scan network infrastructure.
Michael A. Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich
2016Group delay filter measurement using a chirp.
Peter Sarson
2016IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs.
Erik Jan Marinissen, Teresa L. McLaurin, Hailong Jiao
2016IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system.
Jean Durupt, Pascal Vivet, Juergen Schloeffel
2016In situ measurement of aging-induced performance degradation in digital circuits.
Nasim Pour Aryan, Christian Funke, Jens Bargfrede, Cenk Yilmaz, Doris Schmitt-Landsiedel, Georg Georgakos
2016IoT: Source of test challenges.
Erik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes
2016Is IoT coming to the rescue of semiconductor?
Cheng-Wen Wu
2016Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator.
Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda, Guillaume Renaud, Manuel J. Barragán, Salvador Mir
2016Measuring defect tolerance within mixed-signal ICs.
Stephen Sunter, Alessandro Valerio, Riccardo Miglierina
2016On coverage of timing related faults at board level.
Artur Jutman, Igor Aleksejev, Sergei Devadze
2016On the diagnostic analysis of IEEE 1687 networks.
Riccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson
2016Practices in High-Speed IO testing.
Salem Abdennadher, Saghir A. Shaikh
2016Questioning the reliability of Monte Carlo simulation for machine learning test validation.
Gildas Léger, Manuel J. Barragán
2016Read path degradation analysis in SRAM.
Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene
2016Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC.
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue
2016SAT-based post-processing for regional capture power reduction in at-speed scan test generation.
Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen
2016Securely connected vehicles - what it takes to make self-driving cars a reality.
Lars Reger
2016Study of a delayed single-event effect in the Muller C-element.
Varadan Savulimedu Veeravalli, Andreas Steininger
2016Test-station for flexible semi-automatic wafer-level silicon photonics testing.
Jeroen De Coster, Peter De Heyn, Marianna Pantouvaki, Brad Snyder, Hongtao Chen, Erik Jan Marinissen, Philippe Absil, Joris Van Campenhout, Bryan Bolt
2016Testing in the year 2024 - big changes are coming.
Phil Nigh
2016Testing of small delay faults in a clock network.
Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng
2016The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator.
Illani Mohd Nawi, Basel Halak, Mark Zwolinski
2016Transistor stuck-on fault detection tests for digital CMOS circuits.
Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
2016Two-dimensional time-division multiplexing for 3D-SoCs.
Panagiotis Georgiou, Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
2016Utilizing shared memory multi-cores to speed-up the ATPG process.
Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael
2016VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers.
Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler