ETS B

51 papers

YearTitle / Authors
201520th IEEE European Test Symposium, ETS 2015, Cluj-Napoca, Romania, 25-29 May, 2015
2015A Bayesian model for system level reliability estimation.
Alessandro Vallero, Alessandro Savino, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Gianfranco Politano, Dimitris Gizopoulos, Stefano Di Carlo
2015A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs.
Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty
2015A fault tolerant response analyzer with self-error-correction capability.
Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue
2015A low capture power test generation method using capture safe test vectors.
Atsushi Hirai, Yukari Yamauchi, Toshinori Hosokawa, Masayuki Arai
2015A new technique for low-cost phase noise production testing from 1-bit signal acquisition.
Stephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre
2015A practical approach for logic simplification based on fault acceptability for error tolerant application.
Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue
2015A soft-error tolerant TCAM using partial don't-care keys.
Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase
2015Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies.
Yu Huang, Wu Yang, Wu-Tung Cheng
2015Aging guardband reduction through selective flip-flop optimization.
Mohammad Saber Golanbari, Saman Kiamehr, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori
2015An ECC-based memory architecture with online self-repair capabilities for reliability enhancement.
Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato
2015An FPGA-based ATE extension module for low-cost multi-GHz memory test.
David C. Keezer, Te-Hui Chen, Thomas Moon, D. T. Stonecypher, Abhijit Chatterjee, Hyun Woo Choi, Sungyeol Kim, Hosun Yoo
2015An effective hybrid fault-tolerant architecture for pipelined cores.
Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard
2015Analog test: Why still "à la mode" after more than 25 years of research?
Florence Azaïs
2015Automatic generation of autonomous built-in observability structures for analog circuits.
Anthony Coyette, Baris Esen, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen
2015Boundary cost optimization for Alternate Test.
Gildas Léger
2015Branch guided functional test generation at the RTL.
Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao
2015Compact test set generation for test compression-based designs.
Stephan Eggersglüß
2015Cyber-physical systems: A security perspective.
Charalambos Konstantinou, Michail Maniatakos, Fareena Saqib, Shiyan Hu, Jim Plusquellic, Yier Jin
2015Designing area-efficient controllers for multi-cycle transient fault tolerant systems.
Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue
2015Diagnosis of power switches with power-distribution-network consideration.
Vasileios Tenentes, Daniele Rossi, S. Saqib Khursheed, Bashir M. Al-Hashimi
2015Efficient diagnosis technique for aging defects on automotive semiconductor chips.
Jihun Jung, Muhammad Adil Ansari, Dooyoung Kim, Hyunbean Yi, Sungju Park
2015Evaluating the self-testing property of AES' finite field inversion units.
Flavius Opritoiu, Mircea Vladutiu
2015Expanding the boundaries of test and diagnostics: Prognostics and Health Management (PHM) for complex systems.
Douglas Goodman
2015High frequency jitter estimator for SoCs.
Hervé Le Gall, Rshdee Alhakim, Miroslav Valka, Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu
2015Identification of high power consuming areas with gate type and logic level information.
Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
2015Improve the compression ratios for code-based test vector compressions by decomposing.
Jishun Kuang, Liang Zhang, Zhiqiang You, Yingbo Zhou
2015Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases.
Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker
2015Improving test pattern generation in presence of unknown values beyond restricted symbolic logic.
Karsten Scheibler, Dominik Erb, Bernd Becker
2015Is adaptive testing the panacea for the future test problems?
Zebo Peng
2015LSI aging estimation using ring oscillators.
Yukiya Miura, Tatsunori Ikeda
2015Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design.
Ismail Emre Araci, Paul Pop, Krishnendu Chakrabarty
2015NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating.
Daniele Rossi, Vasileios Tenentes, S. Saqib Khursheed, Bashir M. Al-Hashimi
2015New drain current model for nano-meter MOS transistors on-chip threshold voltage test.
Jinbo Wan, Hans G. Kerkhoff
2015On resistive open defect detection in DRAMs: The charge accumulation effect.
Yiorgos Sfikas, Yiorgos Tsiatouhas, Mottaqiallah Taouil, Said Hamdioui
2015On test program compaction.
Marco Gaudesi, Matteo Sonza Reorda, Irith Pomeranz
2015Power-aware voltage tuning for STT-MRAM reliability.
Elena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
2015Protecting caches against multi-bit errors using embedded erasure coding.
Abbas BanaiyanMofrad, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori, Nikil D. Dutt
2015Re-using BIST for circuit aging monitoring.
Farshad Firouzi, Fangming Ye, Arunkumar Vijayan, Abhishek Koneru, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori
2015Reliability analysis for power MOSFET based on multi-physics simulation.
Shuo Li, Hong Wang, Shiyuan Yang
2015Reliability-aware operation chaining in high level synthesis.
Liang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori
2015Robust amplitude measurement for RF BIST applications.
Jae Woong Jeong, Jennifer Kitchen, Sule Ozev
2015Session-less based thermal-aware 3D-SIC test scheduling.
Marie-Lise Flottes, Joao Azevedo, Giorgio Di Natale, Bruno Rouzeyre
2015Software-based repair for memories in tiny embedded systems.
Mario Schölzel, Patryk Skoncej
2015Software-based self-test techniques of computational modules in dual issue embedded processors.
Paolo Bernardi, C. Bovi, Riccardo Cantoro, Sergio de Luca, Renato Meregalli, Davide Piumatti, Ernesto Sánchez, Alessandro Sansonetti
2015Symmetric transparent on-line BIST of word-organized memories with binary adders.
Ioannis Voyiatzis
2015Tackling the complexity of exact path delay fault grading for path intensive circuits.
Stelios N. Neophytou, Maria K. Michael
2015Testing of Analog/Mixed Signal ICs: Past, present and future.
Bram Kruseman
2015Testing of digital microfluidic biochips with arbitrary layouts.
Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty
2015Testing visions.
Hans-Joachim Wunderlich
2015Variability-aware aging modeling for reliability analysis of an analog neural measurement system.
Nils Heidmann, Nico Hellwege, Steffen Paul, Dagmar Peters-Drolshagen