ETS B

27 papers

YearTitle / Authors
200914th IEEE European Test Symposium, ETS 2009, Sevilla, Spain, May 25-29, 2009
2009A Two Phase Approach for Minimal Diagnostic Test Set Generation.
Mohammed Ashfaq Shukoor, Vishwani D. Agrawal
2009A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits.
Josep Rius, Luis Elvira Villagra, Maurice Meijer
2009Algorithms for ADC Multi-site Test with Digital Input Stimulus.
Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido Gronthoud
2009Automatic Functional Stress Pattern Generation for SoC Reliability Characterization.
Davide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso, Edgar E. Sánchez, Matteo Sonza Reorda
2009Built-in Test Solutions for the Electrode Structures in Bio-Fluidic Microsystems.
Qais Al-Gayem, Hongyuan Liu, Andrew Richardson, Nick Burd
2009Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers.
Yasser Sedaghat, Seyed Ghassem Miremadi
2009Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead.
Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich
2009Critical Path Selection for Delay Test Considering Coupling Noise.
Rajeshwary Tayade, Jacob A. Abraham
2009Defect Filter for Alternate RF Test.
Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev
2009Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections.
Olivier Ginez, Jean-Michel Portal, Christophe Muller
2009Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment.
Frank-Uwe Faber, Matthias Beck, Markus Rudack, Olivier Barondeau, Thomas Rabenalt, Michael Gössel, Andreas Leininger
2009Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors.
Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar
2009Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques.
Stephan Eggersglüß, Rolf Drechsler
2009Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation.
Irith Pomeranz, Sudhakar M. Reddy
2009Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip.
Kihyuk Han, Joonsung Park, Jae Wook Lee, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh
2009Masking of X-values by Use of a Hierarchically Configurable Register.
Thomas Rabenalt, Michael Gössel, Andreas Leininger
2009Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive Applications.
Vezio Malandruccolo, Mauro Ciappa, Wolfgang Fichtner, Hubert Rothleitner
2009On Minimization of Peak Power for Scan Circuit during Test.
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal
2009Partial Scan Approach for Secret Information Protection.
Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara
2009Resource-Efficient Programmable Trigger Units for Post-Silicon Validation.
Ho Fai Ko, Nicola Nicolici
2009Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links.
Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada
2009Something I Always Wanted to Know About Test, But Was Afraid to Ask.
Christian Landrault
2009Speed-Path Debug Using At-Speed Scan Test Patterns.
Ruifeng Guo, Wu-Tung Cheng, Kun-Han Tsai
2009Test Encoding for Extreme Response Compaction.
Michael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich
2009Testing of High Resolution ADCs Using Lower Resolution DACs via Iterative Transfer Function Estimation.
Sehun Kook, Vishwanath Natarajan, Abhijit Chatterjee, Shalabh Goyal, Le Jin
2009We Have Got Compression, What Next?
Janusz Rajski